neoverse_n3.h 874 B

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  1. /*
  2. * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #ifndef NEOVERSE_N3_H
  7. #define NEOVERSE_N3_H
  8. #define NEOVERSE_N3_MIDR U(0x410FD8E0)
  9. /*******************************************************************************
  10. * CPU Extended Control register specific definitions
  11. ******************************************************************************/
  12. #define NEOVERSE_N3_CPUECTLR_EL1 S3_0_C15_C1_4
  13. #define NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
  14. /*******************************************************************************
  15. * CPU Power Control register specific definitions
  16. ******************************************************************************/
  17. #define NEOVERSE_N3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
  18. #define NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
  19. #endif /* NEOVERSE_N3_H */