arm_sp_min_setup.c 6.9 KB

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  1. /*
  2. * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <assert.h>
  7. #include <platform_def.h>
  8. #include <bl32/sp_min/platform_sp_min.h>
  9. #include <common/bl_common.h>
  10. #include <common/debug.h>
  11. #include <drivers/console.h>
  12. #include <lib/mmio.h>
  13. #include <plat/arm/common/plat_arm.h>
  14. #include <plat/common/platform.h>
  15. static entry_point_info_t bl33_image_ep_info;
  16. /* Weak definitions may be overridden in specific ARM standard platform */
  17. #pragma weak sp_min_platform_setup
  18. #pragma weak sp_min_plat_arch_setup
  19. #pragma weak plat_arm_sp_min_early_platform_setup
  20. #define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \
  21. BL32_BASE, \
  22. BL32_END - BL32_BASE, \
  23. MT_MEMORY | MT_RW | MT_SECURE)
  24. /*
  25. * Check that BL32_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
  26. * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
  27. */
  28. #if !RESET_TO_SP_MIN
  29. CASSERT(BL32_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl32_base_overflows);
  30. #endif
  31. /*******************************************************************************
  32. * Return a pointer to the 'entry_point_info' structure of the next image for the
  33. * security state specified. BL33 corresponds to the non-secure image type
  34. * while BL32 corresponds to the secure image type. A NULL pointer is returned
  35. * if the image does not exist.
  36. ******************************************************************************/
  37. entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
  38. {
  39. entry_point_info_t *next_image_info;
  40. next_image_info = &bl33_image_ep_info;
  41. /*
  42. * None of the images on the ARM development platforms can have 0x0
  43. * as the entrypoint
  44. */
  45. if (next_image_info->pc)
  46. return next_image_info;
  47. else
  48. return NULL;
  49. }
  50. /*******************************************************************************
  51. * Utility function to perform early platform setup.
  52. ******************************************************************************/
  53. void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
  54. uintptr_t hw_config, void *plat_params_from_bl2)
  55. {
  56. /* Initialize the console to provide early debug support */
  57. arm_console_boot_init();
  58. #if RESET_TO_SP_MIN
  59. /* Populate entry point information for BL33 */
  60. SET_PARAM_HEAD(&bl33_image_ep_info,
  61. PARAM_EP,
  62. VERSION_1,
  63. 0);
  64. /*
  65. * Tell SP_MIN where the non-trusted software image
  66. * is located and the entry state information
  67. */
  68. bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
  69. bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
  70. SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
  71. # if ARM_LINUX_KERNEL_AS_BL33
  72. /*
  73. * According to the file ``Documentation/arm/Booting`` of the Linux
  74. * kernel tree, Linux expects:
  75. * r0 = 0
  76. * r1 = machine type number, optional in DT-only platforms (~0 if so)
  77. * r2 = Physical address of the device tree blob
  78. */
  79. bl33_image_ep_info.args.arg0 = 0U;
  80. bl33_image_ep_info.args.arg1 = ~0U;
  81. bl33_image_ep_info.args.arg2 = (u_register_t)ARM_PRELOADED_DTB_BASE;
  82. # endif
  83. #else /* RESET_TO_SP_MIN */
  84. /*
  85. * Check params passed from BL2 should not be NULL,
  86. */
  87. bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
  88. assert(params_from_bl2 != NULL);
  89. assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
  90. assert(params_from_bl2->h.version >= VERSION_2);
  91. bl_params_node_t *bl_params = params_from_bl2->head;
  92. /*
  93. * Copy BL33 entry point information.
  94. * They are stored in Secure RAM, in BL2's address space.
  95. */
  96. while (bl_params) {
  97. if (bl_params->image_id == BL33_IMAGE_ID) {
  98. bl33_image_ep_info = *bl_params->ep_info;
  99. break;
  100. }
  101. bl_params = bl_params->next_params_info;
  102. }
  103. if (bl33_image_ep_info.pc == 0)
  104. panic();
  105. #endif /* RESET_TO_SP_MIN */
  106. }
  107. /*******************************************************************************
  108. * Default implementation for sp_min_platform_setup2() for ARM platforms
  109. ******************************************************************************/
  110. void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
  111. u_register_t arg2, u_register_t arg3)
  112. {
  113. arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
  114. /*
  115. * Initialize Interconnect for this cluster during cold boot.
  116. * No need for locks as no other CPU is active.
  117. */
  118. plat_arm_interconnect_init();
  119. /*
  120. * Enable Interconnect coherency for the primary CPU's cluster.
  121. * Earlier bootloader stages might already do this (e.g. Trusted
  122. * Firmware's BL1 does it) but we can't assume so. There is no harm in
  123. * executing this code twice anyway.
  124. * Platform specific PSCI code will enable coherency for other
  125. * clusters.
  126. */
  127. plat_arm_interconnect_enter_coherency();
  128. }
  129. void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
  130. u_register_t arg2, u_register_t arg3)
  131. {
  132. plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
  133. }
  134. /*******************************************************************************
  135. * Perform any SP_MIN platform runtime setup prior to SP_MIN exit.
  136. * Common to ARM standard platforms.
  137. ******************************************************************************/
  138. void arm_sp_min_plat_runtime_setup(void)
  139. {
  140. /* Initialize the runtime console */
  141. arm_console_runtime_init();
  142. #if PLAT_RO_XLAT_TABLES
  143. arm_xlat_make_tables_readonly();
  144. #endif
  145. }
  146. /*******************************************************************************
  147. * Perform platform specific setup for SP_MIN
  148. ******************************************************************************/
  149. void sp_min_platform_setup(void)
  150. {
  151. /* Initialize the GIC driver, cpu and distributor interfaces */
  152. plat_arm_gic_driver_init();
  153. plat_arm_gic_init();
  154. /*
  155. * Do initial security configuration to allow DRAM/device access
  156. * (if earlier BL has not already done so).
  157. */
  158. #if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
  159. plat_arm_security_setup();
  160. #if defined(PLAT_ARM_MEM_PROT_ADDR)
  161. arm_nor_psci_do_dyn_mem_protect();
  162. #endif /* PLAT_ARM_MEM_PROT_ADDR */
  163. #endif
  164. /* Enable and initialize the System level generic timer */
  165. #ifdef ARM_SYS_CNTCTL_BASE
  166. mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
  167. CNTCR_FCREQ(0U) | CNTCR_EN);
  168. #endif
  169. #ifdef ARM_SYS_TIMCTL_BASE
  170. /* Allow access to the System counter timer module */
  171. arm_configure_sys_timer();
  172. #endif
  173. /* Initialize power controller before setting up topology */
  174. plat_arm_pwrc_setup();
  175. }
  176. void sp_min_plat_runtime_setup(void)
  177. {
  178. arm_sp_min_plat_runtime_setup();
  179. }
  180. /*******************************************************************************
  181. * Perform the very early platform specific architectural setup here. At the
  182. * moment this only initializes the MMU
  183. ******************************************************************************/
  184. void arm_sp_min_plat_arch_setup(void)
  185. {
  186. const mmap_region_t bl_regions[] = {
  187. MAP_BL_SP_MIN_TOTAL,
  188. ARM_MAP_BL_RO,
  189. #if USE_COHERENT_MEM
  190. ARM_MAP_BL_COHERENT_RAM,
  191. #endif
  192. {0}
  193. };
  194. setup_page_tables(bl_regions, plat_arm_get_mmap());
  195. enable_mmu_svc_mon(0);
  196. }
  197. void sp_min_plat_arch_setup(void)
  198. {
  199. arm_sp_min_plat_arch_setup();
  200. }