tegra_private.h 5.8 KB

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  1. /*
  2. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  3. * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-3-Clause
  6. */
  7. #ifndef TEGRA_PRIVATE_H
  8. #define TEGRA_PRIVATE_H
  9. #include <platform_def.h>
  10. #include <stdbool.h>
  11. #include <arch.h>
  12. #include <arch_helpers.h>
  13. #include <drivers/ti/uart/uart_16550.h>
  14. #include <lib/psci/psci.h>
  15. #include <lib/xlat_tables/xlat_tables_v2.h>
  16. #include <tegra_gic.h>
  17. /*******************************************************************************
  18. * Implementation defined ACTLR_EL1 bit definitions
  19. ******************************************************************************/
  20. #define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0)
  21. /*******************************************************************************
  22. * Implementation defined ACTLR_EL2 bit definitions
  23. ******************************************************************************/
  24. #define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0)
  25. /*******************************************************************************
  26. * Struct for parameters received from BL2
  27. ******************************************************************************/
  28. typedef struct plat_params_from_bl2 {
  29. /* TZ memory size */
  30. uint64_t tzdram_size;
  31. /* TZ memory base */
  32. uint64_t tzdram_base;
  33. /* UART port ID */
  34. int32_t uart_id;
  35. /* L2 ECC parity protection disable flag */
  36. int32_t l2_ecc_parity_prot_dis;
  37. /* SHMEM base address for storing the boot logs */
  38. uint64_t boot_profiler_shmem_base;
  39. /* System Suspend Entry Firmware size */
  40. uint64_t sc7entry_fw_size;
  41. /* System Suspend Entry Firmware base address */
  42. uint64_t sc7entry_fw_base;
  43. /* Enable dual execution */
  44. uint8_t enable_ccplex_lock_step;
  45. } plat_params_from_bl2_t;
  46. /*******************************************************************************
  47. * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs
  48. ******************************************************************************/
  49. DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
  50. /*******************************************************************************
  51. * Struct describing parameters passed to bl31
  52. ******************************************************************************/
  53. struct tegra_bl31_params {
  54. param_header_t h;
  55. image_info_t *bl31_image_info;
  56. entry_point_info_t *bl32_ep_info;
  57. image_info_t *bl32_image_info;
  58. entry_point_info_t *bl33_ep_info;
  59. image_info_t *bl33_image_info;
  60. };
  61. /*******************************************************************************
  62. * To suppress Coverity MISRA C-2012 Rule 2.2 violations
  63. *******************************************************************************/
  64. #define UNUSED_FUNC_NOP() asm("nop")
  65. /* Declarations for plat_psci_handlers.c */
  66. int32_t tegra_soc_validate_power_state(uint32_t power_state,
  67. psci_power_state_t *req_state);
  68. /* Declarations for plat_setup.c */
  69. const mmap_region_t *plat_get_mmio_map(void);
  70. void plat_enable_console(int32_t id);
  71. void plat_gic_setup(void);
  72. struct tegra_bl31_params *plat_get_bl31_params(void);
  73. plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
  74. void plat_early_platform_setup(void);
  75. void plat_late_platform_setup(void);
  76. void plat_relocate_bl32_image(const image_info_t *bl32_img_info);
  77. bool plat_supports_system_suspend(void);
  78. void plat_runtime_setup(void);
  79. /* Declarations for plat_secondary.c */
  80. void plat_secondary_setup(void);
  81. int32_t plat_lock_cpu_vectors(void);
  82. /* Declarations for tegra_fiq_glue.c */
  83. void tegra_fiq_handler_setup(void);
  84. int32_t tegra_fiq_get_intr_context(void);
  85. void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
  86. /* Declarations for tegra_helpers.S */
  87. bool plat_is_my_cpu_primary(void);
  88. /* Declarations for tegra_security.c */
  89. void tegra_security_setup(void);
  90. void tegra_security_setup_videomem(uintptr_t base, uint64_t size);
  91. /* Declarations for tegra_pm.c */
  92. void tegra_pm_system_suspend_entry(void);
  93. void tegra_pm_system_suspend_exit(void);
  94. int32_t tegra_system_suspended(void);
  95. int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state);
  96. int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state);
  97. int32_t tegra_soc_pwr_domain_on(u_register_t mpidr);
  98. int32_t tegra_soc_pwr_domain_off_early(const psci_power_state_t *target_state);
  99. int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state);
  100. int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state);
  101. int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state);
  102. int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state);
  103. int32_t tegra_soc_prepare_system_reset(void);
  104. __dead2 void tegra_soc_prepare_system_off(void);
  105. plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
  106. const plat_local_state_t *states,
  107. uint32_t ncpu);
  108. /* Declarations for tegraXXX_pm.c */
  109. int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl);
  110. int tegra_prepare_cpu_on_finish(unsigned long mpidr);
  111. /* Declarations for tegra_bl31_setup.c */
  112. plat_params_from_bl2_t *bl31_get_plat_params(void);
  113. int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
  114. /* Declarations for tegra_delay_timer.c */
  115. void tegra_delay_timer_init(void);
  116. void tegra_secure_entrypoint(void);
  117. /* Declarations for tegra_sip_calls.c */
  118. uintptr_t tegra_sip_handler(uint32_t smc_fid,
  119. u_register_t x1,
  120. u_register_t x2,
  121. u_register_t x3,
  122. u_register_t x4,
  123. void *cookie,
  124. void *handle,
  125. u_register_t flags);
  126. int plat_sip_handler(uint32_t smc_fid,
  127. uint64_t x1,
  128. uint64_t x2,
  129. uint64_t x3,
  130. uint64_t x4,
  131. const void *cookie,
  132. void *handle,
  133. uint64_t flags);
  134. #if ENABLE_FEAT_RAS && FFH_SUPPORT
  135. void tegra194_ras_enable(void);
  136. void tegra194_ras_corrected_err_clear(uint64_t *cookie);
  137. #endif
  138. #endif /* TEGRA_PRIVATE_H */