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qemu_sbsa_pas_def.h

qemu_sbsa_pas_def.h 2.0 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2024-2025, Linaro Limited. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. #ifndef QEMU_PAS_DEF_H
    7. 

  7. #define QEMU_PAS_DEF_H
    8. 

  8. 

  9. #include <lib/gpt_rme/gpt_rme.h>
    10. 

  10. #include "platform_def.h"
    11. 

  11. 

  12. /*****************************************************************************
    13. 

  13.  * PAS regions used to initialize the Granule Protection Table (GPT)
    14. 

  14.  ****************************************************************************/
    15. 

  15. 

  16. /* EL3 SRAM */
    17. 

  17. #define QEMU_PAS_ROOT_BASE	(BL32_MEM_BASE + BL32_MEM_SIZE)
    18. 

  18. #define QEMU_PAS_ROOT_SIZE	(BL_RAM_SIZE - \
    19. 

  19. 				 (BL32_MEM_SIZE + RME_GPT_DRAM_SIZE))
    20. 

  20. 

  21. /* Secure DRAM */
    22. 

  22. #define QEMU_PAS_SEC_BASE	BL32_MEM_BASE /* BL32_SRAM_BASE */
    23. 

  23. #define QEMU_PAS_SEC_SIZE	BL32_MEM_SIZE
    24. 

  24. 

  25. /* GPTs */
    26. 

  26. #define QEMU_PAS_GPT_BASE	RME_GPT_DRAM_BASE /* PLAT_QEMU_L0_GPT_BASE */
    27. 

  27. #define QEMU_PAS_GPT_SIZE	RME_GPT_DRAM_SIZE
    28. 

  28. 

  29. /* RMM */
    30. 

  30. #define QEMU_PAS_RMM_BASE	RMM_BASE
    31. 

  31. #define QEMU_PAS_RMM_SIZE	PLAT_QEMU_RMM_SIZE
    32. 

  32. 

  33. /* Shared area between EL3 and RMM */
    34. 

  34. #define QEMU_PAS_RMM_SHARED_BASE	RMM_SHARED_BASE
    35. 

  35. #define QEMU_PAS_RMM_SHARED_SIZE	RMM_SHARED_SIZE
    36. 

  36. 

  37. #define QEMU_PAS_ROOT		GPT_MAP_REGION_GRANULE(QEMU_PAS_ROOT_BASE, \
    38. 

  38. 						       QEMU_PAS_ROOT_SIZE, \
    39. 

  39. 						       GPT_GPI_ROOT)
    40. 

  40. 

  41. #define QEMU_PAS_SECURE		GPT_MAP_REGION_GRANULE(QEMU_PAS_SEC_BASE, \
    42. 

  42. 						       QEMU_PAS_SEC_SIZE, \
    43. 

  43. 						       GPT_GPI_SECURE)
    44. 

  44. 

  45. #define QEMU_PAS_GPTS		GPT_MAP_REGION_GRANULE(QEMU_PAS_GPT_BASE, \
    46. 

  46. 						       QEMU_PAS_GPT_SIZE, \
    47. 

  47. 						       GPT_GPI_ROOT)
    48. 

  48. 

  49. /*
    50. 

  50.  * NS0 base address and size are fetched from the DT at runtime.
    51. 

  51.  * See bl31_adjust_pas_regions() for details
    52. 

  52.  */
    53. 

  53. #define QEMU_PAS_NS0		GPT_MAP_REGION_GRANULE(0, 0, GPT_GPI_NS)
    54. 

  54. 

  55. #define QEMU_PAS_REALM		GPT_MAP_REGION_GRANULE(QEMU_PAS_RMM_BASE, \
    56. 

  56. 					       QEMU_PAS_RMM_SIZE + \
    57. 

  57. 					       QEMU_PAS_RMM_SHARED_SIZE, \
    58. 

  58. 					       GPT_GPI_REALM)
    59. 

  59. 

  60. /* Cover 4TB with L0GTP */
    61. 

  61. #define PLATFORM_GPCCR_PPS	GPCCR_PPS_4TB
    62. 

  62. 

  63. /* GPT Configuration options */
    64. 

  64. #define PLATFORM_L0GPTSZ	GPCCR_L0GPTSZ_30BITS
    65. 

  65. 

  66. #endif /* QEMU_PAS_DEF_H */
    67.