pmic_wrap_init.h 2.3 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394
  1. /*
  2. * Copyright (c) 2019, MediaTek Inc. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #ifndef PMIC_WRAP_INIT_H
  7. #define PMIC_WRAP_INIT_H
  8. #include <platform_def.h>
  9. #include <stdint.h>
  10. /* external API */
  11. int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
  12. int32_t pwrap_write(uint32_t adr, uint32_t wdata);
  13. static struct mt8183_pmic_wrap_regs *const mtk_pwrap =
  14. (void *)PMIC_WRAP_BASE;
  15. /* timeout setting */
  16. enum {
  17. TIMEOUT_READ = 255, /* us */
  18. TIMEOUT_WAIT_IDLE = 255 /* us */
  19. };
  20. /* PMIC_WRAP registers */
  21. struct mt8183_pmic_wrap_regs {
  22. uint32_t reserved[776];
  23. uint32_t wacs2_cmd;
  24. uint32_t wacs2_rdata;
  25. uint32_t wacs2_vldclr;
  26. uint32_t reserved1[4];
  27. };
  28. enum {
  29. RDATA_WACS_RDATA_SHIFT = 0,
  30. RDATA_WACS_FSM_SHIFT = 16,
  31. RDATA_WACS_REQ_SHIFT = 19,
  32. RDATA_SYNC_IDLE_SHIFT,
  33. RDATA_INIT_DONE_SHIFT,
  34. RDATA_SYS_IDLE_SHIFT,
  35. };
  36. enum {
  37. RDATA_WACS_RDATA_MASK = 0xffff,
  38. RDATA_WACS_FSM_MASK = 0x7,
  39. RDATA_WACS_REQ_MASK = 0x1,
  40. RDATA_SYNC_IDLE_MASK = 0x1,
  41. RDATA_INIT_DONE_MASK = 0x1,
  42. RDATA_SYS_IDLE_MASK = 0x1,
  43. };
  44. /* WACS_FSM */
  45. enum {
  46. WACS_FSM_IDLE = 0x00,
  47. WACS_FSM_REQ = 0x02,
  48. WACS_FSM_WFDLE = 0x04,
  49. WACS_FSM_WFVLDCLR = 0x06,
  50. WACS_INIT_DONE = 0x01,
  51. WACS_SYNC_IDLE = 0x01,
  52. WACS_SYNC_BUSY = 0x00
  53. };
  54. /* error information flag */
  55. enum {
  56. E_PWR_INVALID_ARG = 1,
  57. E_PWR_INVALID_RW = 2,
  58. E_PWR_INVALID_ADDR = 3,
  59. E_PWR_INVALID_WDAT = 4,
  60. E_PWR_INVALID_OP_MANUAL = 5,
  61. E_PWR_NOT_IDLE_STATE = 6,
  62. E_PWR_NOT_INIT_DONE = 7,
  63. E_PWR_NOT_INIT_DONE_READ = 8,
  64. E_PWR_WAIT_IDLE_TIMEOUT = 9,
  65. E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
  66. E_PWR_INIT_SIDLY_FAIL = 11,
  67. E_PWR_RESET_TIMEOUT = 12,
  68. E_PWR_TIMEOUT = 13,
  69. E_PWR_INIT_RESET_SPI = 20,
  70. E_PWR_INIT_SIDLY = 21,
  71. E_PWR_INIT_REG_CLOCK = 22,
  72. E_PWR_INIT_ENABLE_PMIC = 23,
  73. E_PWR_INIT_DIO = 24,
  74. E_PWR_INIT_CIPHER = 25,
  75. E_PWR_INIT_WRITE_TEST = 26,
  76. E_PWR_INIT_ENABLE_CRC = 27,
  77. E_PWR_INIT_ENABLE_DEWRAP = 28,
  78. E_PWR_INIT_ENABLE_EVENT = 29,
  79. E_PWR_READ_TEST_FAIL = 30,
  80. E_PWR_WRITE_TEST_FAIL = 31,
  81. E_PWR_SWITCH_DIO = 32
  82. };
  83. #endif /* PMIC_WRAP_INIT_H */