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drivers
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renesas
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common
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qos_reg.h

qos_reg.h 4.9 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef QOS_REG_H
    8. 

  8. #define QOS_REG_H
    9. 

  9. 

  10. #define	RCAR_QOS_NONE			3U
    11. 

  11. #define	RCAR_QOS_TYPE_DEFAULT		0U
    12. 

  12. 

  13. #define	RCAR_DRAM_SPLIT_LINEAR		0U
    14. 

  14. #define	RCAR_DRAM_SPLIT_4CH		1U
    15. 

  15. #define	RCAR_DRAM_SPLIT_2CH		2U
    16. 

  16. #define	RCAR_DRAM_SPLIT_AUTO		3U
    17. 

  17. #define	RST_BASE			(0xE6160000U)
    18. 

  18. #define	RST_MODEMR			(RST_BASE + 0x0060U)
    19. 

  19. 

  20. #define	DBSC_BASE			0xE6790000U
    21. 

  21. #define DBSC_DBSYSCNT0			(DBSC_BASE + 0x0100U)
    22. 

  22. #define DBSC_AXARB			(DBSC_BASE + 0x0800U)
    23. 

  23. #define DBSC_DBCAM0CNF1			(DBSC_BASE + 0x0904U)
    24. 

  24. #define DBSC_DBCAM0CNF2			(DBSC_BASE + 0x0908U)
    25. 

  25. #define DBSC_DBCAM0CNF3			(DBSC_BASE + 0x090CU)
    26. 

  26. #define DBSC_DBSCHCNT0			(DBSC_BASE + 0x1000U)
    27. 

  27. #define DBSC_DBSCHCNT1			(DBSC_BASE + 0x1004U)
    28. 

  28. #define DBSC_DBSCHSZ0			(DBSC_BASE + 0x1010U)
    29. 

  29. #define DBSC_DBSCHRW0			(DBSC_BASE + 0x1020U)
    30. 

  30. #define DBSC_DBSCHRW1			(DBSC_BASE + 0x1024U)
    31. 

  31. #define DBSC_DBSCHQOS00			(DBSC_BASE + 0x1030U)
    32. 

  32. #define DBSC_DBSCHQOS01			(DBSC_BASE + 0x1034U)
    33. 

  33. #define DBSC_DBSCHQOS02			(DBSC_BASE + 0x1038U)
    34. 

  34. #define DBSC_DBSCHQOS03			(DBSC_BASE + 0x103CU)
    35. 

  35. #define DBSC_DBSCHQOS40			(DBSC_BASE + 0x1070U)
    36. 

  36. #define DBSC_DBSCHQOS41			(DBSC_BASE + 0x1074U)
    37. 

  37. #define DBSC_DBSCHQOS42			(DBSC_BASE + 0x1078U)
    38. 

  38. #define DBSC_DBSCHQOS43			(DBSC_BASE + 0x107CU)
    39. 

  39. #define DBSC_DBSCHQOS90			(DBSC_BASE + 0x10C0U)
    40. 

  40. #define DBSC_DBSCHQOS91			(DBSC_BASE + 0x10C4U)
    41. 

  41. #define DBSC_DBSCHQOS92			(DBSC_BASE + 0x10C8U)
    42. 

  42. #define DBSC_DBSCHQOS93			(DBSC_BASE + 0x10CCU)
    43. 

  43. #define DBSC_DBSCHQOS120		(DBSC_BASE + 0x10F0U)
    44. 

  44. #define DBSC_DBSCHQOS121		(DBSC_BASE + 0x10F4U)
    45. 

  45. #define DBSC_DBSCHQOS122		(DBSC_BASE + 0x10F8U)
    46. 

  46. #define DBSC_DBSCHQOS123		(DBSC_BASE + 0x10FCU)
    47. 

  47. #define DBSC_DBSCHQOS130		(DBSC_BASE + 0x1100U)
    48. 

  48. #define DBSC_DBSCHQOS131		(DBSC_BASE + 0x1104U)
    49. 

  49. #define DBSC_DBSCHQOS132		(DBSC_BASE + 0x1108U)
    50. 

  50. #define DBSC_DBSCHQOS133		(DBSC_BASE + 0x110CU)
    51. 

  51. #define DBSC_DBSCHQOS140		(DBSC_BASE + 0x1110U)
    52. 

  52. #define DBSC_DBSCHQOS141		(DBSC_BASE + 0x1114U)
    53. 

  53. #define DBSC_DBSCHQOS142		(DBSC_BASE + 0x1118U)
    54. 

  54. #define DBSC_DBSCHQOS143		(DBSC_BASE + 0x111CU)
    55. 

  55. #define DBSC_DBSCHQOS150		(DBSC_BASE + 0x1120U)
    56. 

  56. #define DBSC_DBSCHQOS151		(DBSC_BASE + 0x1124U)
    57. 

  57. #define DBSC_DBSCHQOS152		(DBSC_BASE + 0x1128U)
    58. 

  58. #define DBSC_DBSCHQOS153		(DBSC_BASE + 0x112CU)
    59. 

  59. #define DBSC_SCFCTST0			(DBSC_BASE + 0x1700U)
    60. 

  60. #define DBSC_SCFCTST1			(DBSC_BASE + 0x1708U)
    61. 

  61. #define DBSC_SCFCTST2			(DBSC_BASE + 0x170CU)
    62. 

  62. 

  63. #define	AXI_BASE			0xE6784000U
    64. 

  64. #define	AXI_ADSPLCR0			(AXI_BASE + 0x0008U)
    65. 

  65. #define	AXI_ADSPLCR1			(AXI_BASE + 0x000CU)
    66. 

  66. #define	AXI_ADSPLCR2			(AXI_BASE + 0x0010U)
    67. 

  67. #define	AXI_ADSPLCR3			(AXI_BASE + 0x0014U)
    68. 

  68. #define	AXI_MMCR			(AXI_BASE + 0x0300U)
    69. 

  69. #define	ADSPLCR0_ADRMODE_DEFAULT	((uint32_t)0U << 31U)
    70. 

  70. #define	ADSPLCR0_ADRMODE_GEN2		((uint32_t)1U << 31U)
    71. 

  71. #define	ADSPLCR0_SPLITSEL(x)		((uint32_t)(x) << 16U)
    72. 

  72. #define	ADSPLCR0_AREA(x)		((uint32_t)(x) <<  8U)
    73. 

  73. #define	ADSPLCR0_SWP			0x0CU
    74. 

  74. 

  75. #define	AXI_TR3CR			0xE67D100CU
    76. 

  76. #define	AXI_TR4CR			0xE67D1014U
    77. 

  77. 

  78. #define	QOS_BASE0			0xE67E0000U
    79. 

  79. #define	QOSBW_FIX_QOS_BANK0		(QOS_BASE0 + 0x0000U)
    80. 

  80. #define	QOSBW_FIX_QOS_BANK1		(QOS_BASE0 + 0x1000U)
    81. 

  81. #define	QOSBW_BE_QOS_BANK0		(QOS_BASE0 + 0x2000U)
    82. 

  82. #define	QOSBW_BE_QOS_BANK1		(QOS_BASE0 + 0x3000U)
    83. 

  83. #define	QOSCTRL_SL_INIT			(QOS_BASE0 + 0x8000U)
    84. 

  84. #define	QOSCTRL_REF_ARS			(QOS_BASE0 + 0x8004U)
    85. 

  85. #define	QOSCTRL_STATQC			(QOS_BASE0 + 0x8008U)
    86. 

  86. 

  87. #define	QOS_BASE1			0xE67F0000U
    88. 

  88. #define	QOSCTRL_RAS			(QOS_BASE1 + 0x0000U)
    89. 

  89. #define	QOSCTRL_FIXTH			(QOS_BASE1 + 0x0004U)
    90. 

  90. #define	QOSCTRL_RAEN			(QOS_BASE1 + 0x0018U)
    91. 

  91. #define	QOSCTRL_REGGD			(QOS_BASE1 + 0x0020U)
    92. 

  92. #define	QOSCTRL_DANN			(QOS_BASE1 + 0x0030U)
    93. 

  93. #define	QOSCTRL_DANT			(QOS_BASE1 + 0x0038U)
    94. 

  94. #define	QOSCTRL_EC			(QOS_BASE1 + 0x003CU)
    95. 

  95. #define	QOSCTRL_EMS			(QOS_BASE1 + 0x0040U)
    96. 

  96. #define	QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
    97. 

  97. #define	QOSCTRL_INSFC			(QOS_BASE1 + 0x0050U)
    98. 

  98. #define	QOSCTRL_BERR			(QOS_BASE1 + 0x0054U)
    99. 

  99. #define	QOSCTRL_EARLYR			(QOS_BASE1 + 0x0060U)
    100. 

  100. #define	QOSCTRL_RACNT0			(QOS_BASE1 + 0x0080U)
    101. 

  101. #define	QOSCTRL_STATGEN0		(QOS_BASE1 + 0x0088U)
    102. 

  102. 

  103. #define	GPU_ACT_GRD			0xFD820808U
    104. 

  104. #define	GPU_ACT0			0xFD820800U
    105. 

  105. #define	GPU_ACT1			0xFD821800U
    106. 

  106. #define	GPU_ACT2			0xFD822800U
    107. 

  107. #define	GPU_ACT3			0xFD823800U
    108. 

  108. #define	GPU_ACT4			0xFD824800U
    109. 

  109. #define	GPU_ACT5			0xFD825800U
    110. 

  110. #define	GPU_ACT6			0xFD826800U
    111. 

  111. #define	GPU_ACT7			0xFD827800U
    112. 

  112. 

  113. #define	RT_ACT0				0xFFC50800U
    114. 

  114. #define	RT_ACT1				0xFFC51800U
    115. 

  115. 

  116. #define	CPU_ACT0			0xF1300800U
    117. 

  117. #define	CPU_ACT1			0xF1340800U
    118. 

  118. #define	CPU_ACT2			0xF1380800U
    119. 

  119. #define	CPU_ACT3			0xF13C0800U
    120. 

  120. 

  121. #define	RCAR_REWT_TRAINING_DISABLE	0U
    122. 

  122. #define	RCAR_REWT_TRAINING_ENABLE	1U
    123. 

  123. 

  124. #define QOSWT_FIX_WTQOS_BANK0		(QOSBW_FIX_QOS_BANK0 + 0x0800U)
    125. 

  125. #define QOSWT_FIX_WTQOS_BANK1		(QOSBW_FIX_QOS_BANK1 + 0x0800U)
    126. 

  126. #define QOSWT_BE_WTQOS_BANK0		(QOSBW_BE_QOS_BANK0  + 0x0800U)
    127. 

  127. #define QOSWT_BE_WTQOS_BANK1		(QOSBW_BE_QOS_BANK1  + 0x0800U)
    128. 

  128. #define	QOSWT_WTEN			(QOS_BASE0 + 0x8030U)
    129. 

  129. #define	QOSWT_WTREF			(QOS_BASE0 + 0x8034U)
    130. 

  130. #define	QOSWT_WTSET0			(QOS_BASE0 + 0x8038U)
    131. 

  131. #define	QOSWT_WTSET1			(QOS_BASE0 + 0x803CU)
    132. 

  132. 

  133. #endif /* QOS_REG_H */
    134.