spm_suspend.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255
  1. /*
  2. * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <arch_helpers.h>
  7. #include <common/debug.h>
  8. #include <drivers/delay_timer.h>
  9. #include <mt_gic_v3.h>
  10. #include <lib/mmio.h>
  11. #include <platform_def.h>
  12. #include <pmic.h>
  13. #include <spm.h>
  14. #include <uart.h>
  15. #define SPM_SYSCLK_SETTLE 99
  16. #define WAKE_SRC_FOR_SUSPEND \
  17. (WAKE_SRC_R12_PCM_TIMER | \
  18. WAKE_SRC_R12_SSPM_WDT_EVENT_B | \
  19. WAKE_SRC_R12_KP_IRQ_B | \
  20. WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B | \
  21. WAKE_SRC_R12_EINT_EVENT_B | \
  22. WAKE_SRC_R12_CONN_WDT_IRQ_B | \
  23. WAKE_SRC_R12_CCIF0_EVENT_B | \
  24. WAKE_SRC_R12_SSPM_SPM_IRQ_B | \
  25. WAKE_SRC_R12_SCP_SPM_IRQ_B | \
  26. WAKE_SRC_R12_SCP_WDT_EVENT_B | \
  27. WAKE_SRC_R12_USB_CDSC_B | \
  28. WAKE_SRC_R12_USB_POWERDWN_B | \
  29. WAKE_SRC_R12_SYS_TIMER_EVENT_B | \
  30. WAKE_SRC_R12_EINT_EVENT_SECURE_B | \
  31. WAKE_SRC_R12_CCIF1_EVENT_B | \
  32. WAKE_SRC_R12_MD2AP_PEER_EVENT_B | \
  33. WAKE_SRC_R12_MD1_WDT_B | \
  34. WAKE_SRC_R12_CLDMA_EVENT_B | \
  35. WAKE_SRC_R12_SEJ_WDT_GPT_B)
  36. #define SLP_PCM_FLAGS \
  37. (SPM_FLAG_DIS_VCORE_DVS | SPM_FLAG_DIS_VCORE_DFS | \
  38. SPM_FLAG_DIS_ATF_ABORT | SPM_FLAG_DISABLE_MMSYS_DVFS | \
  39. SPM_FLAG_DIS_INFRA_PDN | SPM_FLAG_SUSPEND_OPTION)
  40. #define SLP_PCM_FLAGS1 \
  41. (SPM_FLAG1_DISABLE_MCDSR)
  42. static const struct pwr_ctrl suspend_ctrl = {
  43. .wake_src = WAKE_SRC_FOR_SUSPEND,
  44. .pcm_flags = SLP_PCM_FLAGS,
  45. .pcm_flags1 = SLP_PCM_FLAGS1,
  46. /* SPM_AP_STANDBY_CON */
  47. .wfi_op = 0x1,
  48. .mp0_cputop_idle_mask = 0,
  49. .mp1_cputop_idle_mask = 0,
  50. .mcusys_idle_mask = 0,
  51. .mm_mask_b = 0,
  52. .md_ddr_en_0_dbc_en = 0x1,
  53. .md_ddr_en_1_dbc_en = 0,
  54. .md_mask_b = 0x1,
  55. .sspm_mask_b = 0x1,
  56. .scp_mask_b = 0x1,
  57. .srcclkeni_mask_b = 0x1,
  58. .md_apsrc_1_sel = 0,
  59. .md_apsrc_0_sel = 0,
  60. .conn_ddr_en_dbc_en = 0x1,
  61. .conn_mask_b = 0x1,
  62. .conn_apsrc_sel = 0,
  63. /* SPM_SRC_REQ */
  64. .spm_apsrc_req = 0,
  65. .spm_f26m_req = 0,
  66. .spm_infra_req = 0,
  67. .spm_vrf18_req = 0,
  68. .spm_ddren_req = 0,
  69. .spm_rsv_src_req = 0,
  70. .spm_ddren_2_req = 0,
  71. .cpu_md_dvfs_sop_force_on = 0,
  72. /* SPM_SRC_MASK */
  73. .csyspwreq_mask = 0x1,
  74. .ccif0_md_event_mask_b = 0x1,
  75. .ccif0_ap_event_mask_b = 0x1,
  76. .ccif1_md_event_mask_b = 0x1,
  77. .ccif1_ap_event_mask_b = 0x1,
  78. .ccif2_md_event_mask_b = 0x1,
  79. .ccif2_ap_event_mask_b = 0x1,
  80. .ccif3_md_event_mask_b = 0x1,
  81. .ccif3_ap_event_mask_b = 0x1,
  82. .md_srcclkena_0_infra_mask_b = 0x1,
  83. .md_srcclkena_1_infra_mask_b = 0,
  84. .conn_srcclkena_infra_mask_b = 0,
  85. .ufs_infra_req_mask_b = 0,
  86. .srcclkeni_infra_mask_b = 0,
  87. .md_apsrc_req_0_infra_mask_b = 0x1,
  88. .md_apsrc_req_1_infra_mask_b = 0x1,
  89. .conn_apsrcreq_infra_mask_b = 0x1,
  90. .ufs_srcclkena_mask_b = 0,
  91. .md_vrf18_req_0_mask_b = 0,
  92. .md_vrf18_req_1_mask_b = 0,
  93. .ufs_vrf18_req_mask_b = 0,
  94. .gce_vrf18_req_mask_b = 0,
  95. .conn_infra_req_mask_b = 0x1,
  96. .gce_apsrc_req_mask_b = 0,
  97. .disp0_apsrc_req_mask_b = 0,
  98. .disp1_apsrc_req_mask_b = 0,
  99. .mfg_req_mask_b = 0,
  100. .vdec_req_mask_b = 0,
  101. /* SPM_SRC2_MASK */
  102. .md_ddr_en_0_mask_b = 0x1,
  103. .md_ddr_en_1_mask_b = 0,
  104. .conn_ddr_en_mask_b = 0x1,
  105. .ddren_sspm_apsrc_req_mask_b = 0x1,
  106. .ddren_scp_apsrc_req_mask_b = 0x1,
  107. .disp0_ddren_mask_b = 0x1,
  108. .disp1_ddren_mask_b = 0x1,
  109. .gce_ddren_mask_b = 0x1,
  110. .ddren_emi_self_refresh_ch0_mask_b = 0,
  111. .ddren_emi_self_refresh_ch1_mask_b = 0,
  112. /* SPM_WAKEUP_EVENT_MASK */
  113. .spm_wakeup_event_mask = 0xF1782218,
  114. /* SPM_WAKEUP_EVENT_EXT_MASK */
  115. .spm_wakeup_event_ext_mask = 0xFFFFFFFF,
  116. /* SPM_SRC3_MASK */
  117. .md_ddr_en_2_0_mask_b = 0x1,
  118. .md_ddr_en_2_1_mask_b = 0,
  119. .conn_ddr_en_2_mask_b = 0x1,
  120. .ddren2_sspm_apsrc_req_mask_b = 0x1,
  121. .ddren2_scp_apsrc_req_mask_b = 0x1,
  122. .disp0_ddren2_mask_b = 0,
  123. .disp1_ddren2_mask_b = 0,
  124. .gce_ddren2_mask_b = 0,
  125. .ddren2_emi_self_refresh_ch0_mask_b = 0,
  126. .ddren2_emi_self_refresh_ch1_mask_b = 0,
  127. .mp0_cpu0_wfi_en = 0x1,
  128. .mp0_cpu1_wfi_en = 0x1,
  129. .mp0_cpu2_wfi_en = 0x1,
  130. .mp0_cpu3_wfi_en = 0x1,
  131. .mp1_cpu0_wfi_en = 0x1,
  132. .mp1_cpu1_wfi_en = 0x1,
  133. .mp1_cpu2_wfi_en = 0x1,
  134. .mp1_cpu3_wfi_en = 0x1
  135. };
  136. static uint32_t spm_set_sysclk_settle(void)
  137. {
  138. mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE);
  139. return mmio_read_32(SPM_CLK_SETTLE);
  140. }
  141. void go_to_sleep_before_wfi(void)
  142. {
  143. int cpu = MPIDR_AFFLVL0_VAL(read_mpidr());
  144. uint32_t settle;
  145. settle = spm_set_sysclk_settle();
  146. spm_set_cpu_status(cpu);
  147. spm_set_power_control(&suspend_ctrl);
  148. spm_set_wakeup_event(&suspend_ctrl);
  149. spm_set_pcm_flags(&suspend_ctrl);
  150. spm_send_cpu_wakeup_event();
  151. spm_set_pcm_wdt(0);
  152. spm_disable_pcm_timer();
  153. if (is_infra_pdn(suspend_ctrl.pcm_flags))
  154. mt_uart_save();
  155. if (!mt_console_uart_cg_status())
  156. console_switch_state(CONSOLE_FLAG_BOOT);
  157. INFO("cpu%d: \"%s\", wakesrc = 0x%x, pcm_con1 = 0x%x\n",
  158. cpu, spm_get_firmware_version(), suspend_ctrl.wake_src,
  159. mmio_read_32(PCM_CON1));
  160. INFO("settle = %u, sec = %u, sw_flag = 0x%x 0x%x, src_req = 0x%x\n",
  161. settle, mmio_read_32(PCM_TIMER_VAL) / 32768,
  162. suspend_ctrl.pcm_flags, suspend_ctrl.pcm_flags1,
  163. mmio_read_32(SPM_SRC_REQ));
  164. if (!mt_console_uart_cg_status())
  165. console_switch_state(CONSOLE_FLAG_RUNTIME);
  166. }
  167. static void go_to_sleep_after_wfi(void)
  168. {
  169. struct wake_status spm_wakesta;
  170. if (is_infra_pdn(suspend_ctrl.pcm_flags))
  171. mt_uart_restore();
  172. spm_set_pcm_wdt(0);
  173. spm_get_wakeup_status(&spm_wakesta);
  174. spm_clean_after_wakeup();
  175. if (!mt_console_uart_cg_status())
  176. console_switch_state(CONSOLE_FLAG_BOOT);
  177. spm_output_wake_reason(&spm_wakesta, "suspend");
  178. if (!mt_console_uart_cg_status())
  179. console_switch_state(CONSOLE_FLAG_RUNTIME);
  180. }
  181. static void spm_enable_armpll_l(void)
  182. {
  183. /* power on */
  184. mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x1);
  185. /* clear isolation */
  186. mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x2);
  187. /* enable pll */
  188. mmio_setbits_32(ARMPLL_L_CON0, 0x1);
  189. /* Add 20us delay for turning on PLL */
  190. udelay(20);
  191. }
  192. static void spm_disable_armpll_l(void)
  193. {
  194. /* disable pll */
  195. mmio_clrbits_32(ARMPLL_L_CON0, 0x1);
  196. /* isolation */
  197. mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x2);
  198. /* power off */
  199. mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x1);
  200. }
  201. void spm_system_suspend(void)
  202. {
  203. spm_disable_armpll_l();
  204. bcpu_enable(0);
  205. bcpu_sram_enable(0);
  206. spm_lock_get();
  207. go_to_sleep_before_wfi();
  208. spm_lock_release();
  209. }
  210. void spm_system_suspend_finish(void)
  211. {
  212. spm_lock_get();
  213. go_to_sleep_after_wfi();
  214. spm_lock_release();
  215. spm_enable_armpll_l();
  216. bcpu_sram_enable(1);
  217. bcpu_enable(1);
  218. }