mtk_dcm.c 1.4 KB

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  1. /*
  2. * Copyright (c) 2020, MediaTek Inc. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <mtk_dcm.h>
  7. #include <mtk_dcm_utils.h>
  8. static void dcm_armcore(bool mode)
  9. {
  10. dcm_mp_cpusys_top_bus_pll_div_dcm(mode);
  11. dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode);
  12. dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode);
  13. }
  14. static void dcm_mcusys(bool on)
  15. {
  16. dcm_mp_cpusys_top_adb_dcm(on);
  17. dcm_mp_cpusys_top_apb_dcm(on);
  18. dcm_mp_cpusys_top_cpubiu_dcm(on);
  19. dcm_mp_cpusys_top_misc_dcm(on);
  20. dcm_mp_cpusys_top_mp0_qdcm(on);
  21. dcm_cpccfg_reg_emi_wfifo(on);
  22. dcm_mp_cpusys_top_last_cor_idle_dcm(on);
  23. }
  24. static void dcm_stall(bool on)
  25. {
  26. dcm_mp_cpusys_top_core_stall_dcm(on);
  27. dcm_mp_cpusys_top_fcm_stall_dcm(on);
  28. }
  29. static bool check_dcm_state(void)
  30. {
  31. bool ret = true;
  32. ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on();
  33. ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on();
  34. ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on();
  35. ret &= dcm_mp_cpusys_top_adb_dcm_is_on();
  36. ret &= dcm_mp_cpusys_top_apb_dcm_is_on();
  37. ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on();
  38. ret &= dcm_mp_cpusys_top_misc_dcm_is_on();
  39. ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on();
  40. ret &= dcm_cpccfg_reg_emi_wfifo_is_on();
  41. ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on();
  42. ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on();
  43. ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on();
  44. return ret;
  45. }
  46. bool dcm_set_default(void)
  47. {
  48. dcm_armcore(true);
  49. dcm_mcusys(true);
  50. dcm_stall(true);
  51. return check_dcm_state();
  52. }