mt_spm_rc_syspll.c 4.8 KB

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  1. /*
  2. * Copyright (c) 2021, MediaTek Inc. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <common/debug.h>
  7. #include <mt_lp_rm.h>
  8. #include <mt_spm.h>
  9. #include <mt_spm_cond.h>
  10. #include <mt_spm_constraint.h>
  11. #include <mt_spm_conservation.h>
  12. #include <mt_spm_idle.h>
  13. #include <mt_spm_internal.h>
  14. #include <mt_spm_notifier.h>
  15. #include <mt_spm_rc_internal.h>
  16. #include <mt_spm_reg.h>
  17. #include <mt_spm_resource_req.h>
  18. #include <mt_spm_suspend.h>
  19. #include <plat_pm.h>
  20. #include <plat_mtk_lpm.h>
  21. #define CONSTRAINT_SYSPLL_ALLOW \
  22. (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
  23. MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
  24. MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
  25. MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
  26. #define CONSTRAINT_SYSPLL_PCM_FLAG \
  27. (SPM_FLAG_DISABLE_INFRA_PDN | \
  28. SPM_FLAG_DISABLE_VCORE_DVS | \
  29. SPM_FLAG_DISABLE_VCORE_DFS | \
  30. SPM_FLAG_SRAM_SLEEP_CTRL | \
  31. SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
  32. SPM_FLAG_ENABLE_6315_CTRL | \
  33. SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |\
  34. SPM_FLAG_USE_SRCCLKENO2)
  35. #define CONSTRAINT_SYSPLL_PCM_FLAG1 0U
  36. #define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
  37. static struct mt_spm_cond_tables cond_syspll = {
  38. .name = "syspll",
  39. .table_cg = {
  40. 0xFFFFD008, /* MTCMOS1 */
  41. 0x20844802, /* INFRA0 */
  42. 0x27AF8000, /* INFRA1 */
  43. 0x86040640, /* INFRA2 */
  44. 0x30038020, /* INFRA3 */
  45. 0x80000000, /* INFRA4 */
  46. 0x00080A8B, /* PERI0 */
  47. 0x00004000, /* VPPSYS0_0 */
  48. 0x08803000, /* VPPSYS0_1 */
  49. 0x00000000, /* VPPSYS0_2 */
  50. 0x80005555, /* VPPSYS1_0 */
  51. 0x00009008, /* VPPSYS1_1 */
  52. 0x60060000, /* VDOSYS0_0 */
  53. 0x00000000, /* VDOSYS0_1 */
  54. 0x201E01F8, /* VDOSYS1_0 */
  55. 0x00800000, /* VDOSYS1_1 */
  56. 0x00000000, /* VDOSYS1_2 */
  57. 0x00000080, /* I2C */
  58. },
  59. .table_pll = 0U,
  60. };
  61. static struct mt_spm_cond_tables cond_syspll_res = {
  62. .table_cg = { 0U },
  63. .table_pll = 0U,
  64. };
  65. static struct constraint_status status = {
  66. .id = MT_RM_CONSTRAINT_ID_SYSPLL,
  67. .valid = (MT_SPM_RC_VALID_SW |
  68. MT_SPM_RC_VALID_COND_LATCH |
  69. MT_SPM_RC_VALID_XSOC_BBLPM),
  70. .cond_block = 0U,
  71. .enter_cnt = 0U,
  72. .cond_res = &cond_syspll_res,
  73. };
  74. static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
  75. unsigned int *resource_req)
  76. {
  77. spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
  78. spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
  79. *resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
  80. }
  81. bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
  82. {
  83. (void)cpu;
  84. (void)state_id;
  85. return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
  86. }
  87. int spm_update_rc_syspll(int state_id, int type, const void *val)
  88. {
  89. const struct mt_spm_cond_tables *tlb;
  90. const struct mt_spm_cond_tables *tlb_check;
  91. int res = MT_RM_STATUS_OK;
  92. if (val == NULL) {
  93. return MT_RM_STATUS_BAD;
  94. }
  95. if (type == PLAT_RC_UPDATE_CONDITION) {
  96. tlb = (const struct mt_spm_cond_tables *)val;
  97. tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
  98. status.cond_block =
  99. mt_spm_cond_check(state_id, tlb, tlb_check,
  100. ((status.valid &
  101. MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
  102. &cond_syspll_res : NULL);
  103. } else {
  104. res = MT_RM_STATUS_BAD;
  105. }
  106. return res;
  107. }
  108. unsigned int spm_allow_rc_syspll(int state_id)
  109. {
  110. (void)state_id;
  111. return CONSTRAINT_SYSPLL_ALLOW;
  112. }
  113. int spm_run_rc_syspll(unsigned int cpu, int state_id)
  114. {
  115. unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
  116. unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
  117. (void)cpu;
  118. if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
  119. #ifdef MT_SPM_USING_SRCLKEN_RC
  120. ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
  121. #else
  122. allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
  123. #endif
  124. }
  125. #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
  126. mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
  127. (IS_PLAT_SUSPEND_ID(state_id) ?
  128. MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
  129. #else
  130. (void)allows;
  131. #endif
  132. if (IS_PLAT_SUSPEND_ID(state_id)) {
  133. mt_spm_suspend_enter(state_id,
  134. (MT_SPM_EX_OP_SET_WDT |
  135. MT_SPM_EX_OP_HW_S1_DETECT |
  136. MT_SPM_EX_OP_SET_SUSPEND_MODE),
  137. CONSTRAINT_SYSPLL_RESOURCE_REQ);
  138. } else {
  139. mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
  140. }
  141. return 0;
  142. }
  143. int spm_reset_rc_syspll(unsigned int cpu, int state_id)
  144. {
  145. unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
  146. unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
  147. (void)cpu;
  148. if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
  149. #ifdef MT_SPM_USING_SRCLKEN_RC
  150. ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
  151. #else
  152. allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
  153. #endif
  154. }
  155. #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
  156. mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
  157. #else
  158. (void)allows;
  159. #endif
  160. if (IS_PLAT_SUSPEND_ID(state_id)) {
  161. mt_spm_suspend_resume(state_id,
  162. (MT_SPM_EX_OP_SET_SUSPEND_MODE |
  163. MT_SPM_EX_OP_SET_WDT |
  164. MT_SPM_EX_OP_HW_S1_DETECT),
  165. NULL);
  166. } else {
  167. mt_spm_idle_generic_resume(state_id, ext_op, NULL);
  168. status.enter_cnt++;
  169. }
  170. return 0;
  171. }