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plat
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mediatek
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mt8196
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drivers
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gpio
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mtgpio.c

mtgpio.c 1.3 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2024, MediaTek Inc. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #include <assert.h>
    8. 

  8. #include <platform_def.h>
    9. 

  9. #include <mtgpio.h>
    10. 

  10. 

  11. typedef enum {
    12. 

  12. 	REG_0 = 0,
    13. 

  13. 	REG_1,
    14. 

  14. 	REG_2,
    15. 

  15. 	REG_3,
    16. 

  16. 	REG_4,
    17. 

  17. 	REG_5,
    18. 

  18. 	REG_6,
    19. 

  19. 	REG_7,
    20. 

  20. 	REG_8,
    21. 

  21. 	REG_9,
    22. 

  22. 	REG_10,
    23. 

  23. 	REG_11,
    24. 

  24. 	REG_12,
    25. 

  25. 	REG_13,
    26. 

  26. 	REG_14
    27. 

  27. } RegEnum;
    28. 

  28. 

  29. uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
    30. 

  30. {
    31. 

  31. 	uintptr_t reg_addr = 0U;
    32. 

  32. 	struct mt_pin_info gpio_info;
    33. 

  33. 

  34. 	assert(pin < MAX_GPIO_PIN);
    35. 

  35. 

  36. 	gpio_info = mt_pin_infos[pin];
    37. 

  37. 

  38. 	switch (gpio_info.base & 0xF) {
    39. 

  39. 	case REG_0:
    40. 

  40. 		reg_addr = IOCFG_RT_BASE;
    41. 

  41. 		break;
    42. 

  42. 	case REG_1:
    43. 

  43. 		reg_addr = IOCFG_RM1_BASE;
    44. 

  44. 		break;
    45. 

  45. 	case REG_2:
    46. 

  46. 		reg_addr = IOCFG_RM2_BASE;
    47. 

  47. 		break;
    48. 

  48. 	case REG_3:
    49. 

  49. 		reg_addr = IOCFG_RB_BASE;
    50. 

  50. 		break;
    51. 

  51. 	case REG_4:
    52. 

  52. 		reg_addr = IOCFG_BM1_BASE;
    53. 

  53. 		break;
    54. 

  54. 	case REG_5:
    55. 

  55. 		reg_addr = IOCFG_BM2_BASE;
    56. 

  56. 		break;
    57. 

  57. 	case REG_6:
    58. 

  58. 		reg_addr = IOCFG_BM3_BASE;
    59. 

  59. 		break;
    60. 

  60. 	case REG_7:
    61. 

  61. 		reg_addr = IOCFG_LT_BASE;
    62. 

  62. 		break;
    63. 

  63. 	case REG_8:
    64. 

  64. 		reg_addr = IOCFG_LM1_BASE;
    65. 

  65. 		break;
    66. 

  66. 	case REG_9:
    67. 

  67. 		reg_addr = IOCFG_LM2_BASE;
    68. 

  68. 		break;
    69. 

  69. 	case REG_10:
    70. 

  70. 		reg_addr = IOCFG_LB1_BASE;
    71. 

  71. 		break;
    72. 

  72. 	case REG_11:
    73. 

  73. 		reg_addr = IOCFG_LB2_BASE;
    74. 

  74. 		break;
    75. 

  75. 	case REG_12:
    76. 

  76. 		reg_addr = IOCFG_TM1_BASE;
    77. 

  77. 		break;
    78. 

  78. 	case REG_13:
    79. 

  79. 		reg_addr = IOCFG_TM2_BASE;
    80. 

  80. 		break;
    81. 

  81. 	case REG_14:
    82. 

  82. 		reg_addr = IOCFG_TM3_BASE;
    83. 

  83. 		break;
    84. 

  84. 	default:
    85. 

  85. 		break;
    86. 

  86. 	}
    87. 

  87. 

  88. 	return reg_addr;
    89. 

  89. }
    90.