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platform_def.h

platform_def.h 9.3 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2024, Mediatek Inc. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef PLATFORM_DEF_H
    8. 

  8. #define PLATFORM_DEF_H
    9. 

  9. 

  10. #include <arch.h>
    11. 

  11. #include <plat/common/common_def.h>
    12. 

  12. 

  13. #include <arch_def.h>
    14. 

  14. 

  15. #define PLAT_PRIMARY_CPU	(0x0)
    16. 

  16. 

  17. #define MT_GIC_BASE		(0x0C400000)
    18. 

  18. #define MCUCFG_BASE		(0x0C000000)
    19. 

  19. #define MCUCFG_REG_SIZE		(0x50000)
    20. 

  20. #define IO_PHYS			(0x10000000)
    21. 

  21. 

  22. /* Aggregate of all devices for MMU mapping */
    23. 

  23. #define MTK_DEV_RNG1_BASE	(IO_PHYS)
    24. 

  24. #define MTK_DEV_RNG1_SIZE	(0x10000000)
    25. 

  25. 

  26. #define TOPCKGEN_BASE		(IO_PHYS)
    27. 

  27. 

  28. /*******************************************************************************
    29. 

  29.  * AUDIO related constants
    30. 

  30.  ******************************************************************************/
    31. 

  31. #define AUDIO_BASE		(IO_PHYS + 0x0a110000)
    32. 

  32. 

  33. /*******************************************************************************
    34. 

  34.  * APUSYS related constants
    35. 

  35.  ******************************************************************************/
    36. 

  36. #define APUSYS_BASE			(IO_PHYS + 0x09000000)
    37. 

  37. #define APU_MD32_SYSCTRL		(IO_PHYS + 0x09001000)
    38. 

  38. #define APU_MD32_WDT			(IO_PHYS + 0x09002000)
    39. 

  39. #define APU_LOGTOP			(IO_PHYS + 0x09024000)
    40. 

  40. #define APUSYS_CTRL_DAPC_RCX_BASE	(IO_PHYS + 0x09030000)
    41. 

  41. #define APU_REVISER			(IO_PHYS + 0x0903C000)
    42. 

  42. #define APU_RCX_UPRV_TCU		(IO_PHYS + 0x09060000)
    43. 

  43. #define APU_RCX_EXTM_TCU		(IO_PHYS + 0x09061000)
    44. 

  44. #define APU_CMU_TOP			(IO_PHYS + 0x09067000)
    45. 

  45. #define APUSYS_CE_BASE			(IO_PHYS + 0x090B0000)
    46. 

  46. #define APU_ARE_REG_BASE		(IO_PHYS + 0x090B0000)
    47. 

  47. #define APU_RCX_VCORE_CONFIG		(IO_PHYS + 0x090E0000)
    48. 

  48. #define APU_AO_CTRL			(IO_PHYS + 0x090F2000)
    49. 

  49. #define APU_SEC_CON			(IO_PHYS + 0x090F5000)
    50. 

  50. #define APUSYS_CTRL_DAPC_AO_BASE	(IO_PHYS + 0x090FC000)
    51. 

  51. 

  52. #define APU_MBOX0			(0x4C200000)
    53. 

  53. #define APU_MD32_TCM			(0x4D000000)
    54. 

  54. 

  55. #define APU_MD32_TCM_SZ			(0x50000)
    56. 

  56. #define APU_MBOX0_SZ			(0x100000)
    57. 

  57. #define APU_INFRA_BASE			(0x1002C000)
    58. 

  58. #define APU_INFRA_SZ			(0x1000)
    59. 

  59. 

  60. #define APU_RESERVE_MEMORY		(0x95000000)
    61. 

  61. #define APU_SEC_INFO_OFFSET		(0x100000)
    62. 

  62. #define APU_RESERVE_SIZE		(0x1400000)
    63. 

  63. 

  64. /*******************************************************************************
    65. 

  65.  * SPM related constants
    66. 

  66.  ******************************************************************************/
    67. 

  67. #define SPM_BASE		(IO_PHYS + 0x0C004000)
    68. 

  68. 

  69. /*******************************************************************************
    70. 

  70.  * GPIO related constants
    71. 

  71.  ******************************************************************************/
    72. 

  72. #define GPIO_BASE		(IO_PHYS + 0x0002D000)
    73. 

  73. #define RGU_BASE		(IO_PHYS + 0x0C00B000)
    74. 

  74. #define DRM_BASE		(IO_PHYS + 0x0000D000)
    75. 

  75. #define IOCFG_RT_BASE		(IO_PHYS + 0x02000000)
    76. 

  76. #define IOCFG_RM1_BASE		(IO_PHYS + 0x02020000)
    77. 

  77. #define IOCFG_RM2_BASE		(IO_PHYS + 0x02040000)
    78. 

  78. #define IOCFG_RB_BASE		(IO_PHYS + 0x02060000)
    79. 

  79. #define IOCFG_BM1_BASE		(IO_PHYS + 0x02820000)
    80. 

  80. #define IOCFG_BM2_BASE		(IO_PHYS + 0x02840000)
    81. 

  81. #define IOCFG_BM3_BASE		(IO_PHYS + 0x02860000)
    82. 

  82. #define IOCFG_LT_BASE		(IO_PHYS + 0x03000000)
    83. 

  83. #define IOCFG_LM1_BASE		(IO_PHYS + 0x03020000)
    84. 

  84. #define IOCFG_LM2_BASE		(IO_PHYS + 0x03040000)
    85. 

  85. #define IOCFG_LB1_BASE		(IO_PHYS + 0x030f0000)
    86. 

  86. #define IOCFG_LB2_BASE		(IO_PHYS + 0x03110000)
    87. 

  87. #define IOCFG_TM1_BASE		(IO_PHYS + 0x03800000)
    88. 

  88. #define IOCFG_TM2_BASE		(IO_PHYS + 0x03820000)
    89. 

  89. #define IOCFG_TM3_BASE		(IO_PHYS + 0x03860000)
    90. 

  90. 

  91. /*******************************************************************************
    92. 

  92.  * UART related constants
    93. 

  93.  ******************************************************************************/
    94. 

  94. #define UART0_BASE	(IO_PHYS + 0x06000000)
    95. 

  95. #define UART_BAUDRATE	(115200)
    96. 

  96. 

  97. /*******************************************************************************
    98. 

  98.  * Infra IOMMU related constants
    99. 

  99.  ******************************************************************************/
    100. 

  100. #define INFRACFG_AO_BASE	(IO_PHYS + 0x00001000)
    101. 

  101. #define INFRACFG_AO_MEM_BASE	(IO_PHYS + 0x00404000)
    102. 

  102. #define PERICFG_AO_BASE		(IO_PHYS + 0x06630000)
    103. 

  103. #define PERICFG_AO_REG_SIZE	(0x1000)
    104. 

  104. 

  105. /*******************************************************************************
    106. 

  106.  * GIC-600 & interrupt handling related constants
    107. 

  107.  ******************************************************************************/
    108. 

  108. /* Base MTK_platform compatible GIC memory map */
    109. 

  109. #define BASE_GICD_BASE		(MT_GIC_BASE)
    110. 

  110. #define MT_GIC_RDIST_BASE	(MT_GIC_BASE + 0x40000)
    111. 

  111. #define MTK_GIC_REG_SIZE	0x400000
    112. 

  112. 

  113. /*******************************************************************************
    114. 

  114.  * MM IOMMU & SMI related constants
    115. 

  115.  ******************************************************************************/
    116. 

  116. #define SMI_LARB_0_BASE		(IO_PHYS + 0x0c022000)
    117. 

  117. #define SMI_LARB_1_BASE		(IO_PHYS + 0x0c023000)
    118. 

  118. #define SMI_LARB_2_BASE		(IO_PHYS + 0x0c102000)
    119. 

  119. #define SMI_LARB_3_BASE		(IO_PHYS + 0x0c103000)
    120. 

  120. #define SMI_LARB_4_BASE		(IO_PHYS + 0x04013000)
    121. 

  121. #define SMI_LARB_5_BASE		(IO_PHYS + 0x04f02000)
    122. 

  122. #define SMI_LARB_6_BASE		(IO_PHYS + 0x04f03000)
    123. 

  123. #define SMI_LARB_7_BASE		(IO_PHYS + 0x04e04000)
    124. 

  124. #define SMI_LARB_9_BASE		(IO_PHYS + 0x05001000)
    125. 

  125. #define SMI_LARB_10_BASE	(IO_PHYS + 0x05120000)
    126. 

  126. #define SMI_LARB_11A_BASE	(IO_PHYS + 0x05230000)
    127. 

  127. #define SMI_LARB_11B_BASE	(IO_PHYS + 0x05530000)
    128. 

  128. #define SMI_LARB_11C_BASE	(IO_PHYS + 0x05630000)
    129. 

  129. #define SMI_LARB_12_BASE	(IO_PHYS + 0x05340000)
    130. 

  130. #define SMI_LARB_13_BASE	(IO_PHYS + 0x06001000)
    131. 

  131. #define SMI_LARB_14_BASE	(IO_PHYS + 0x06002000)
    132. 

  132. #define SMI_LARB_15_BASE	(IO_PHYS + 0x05140000)
    133. 

  133. #define SMI_LARB_16A_BASE	(IO_PHYS + 0x06008000)
    134. 

  134. #define SMI_LARB_16B_BASE	(IO_PHYS + 0x0600a000)
    135. 

  135. #define SMI_LARB_17A_BASE	(IO_PHYS + 0x06009000)
    136. 

  136. #define SMI_LARB_17B_BASE	(IO_PHYS + 0x0600b000)
    137. 

  137. #define SMI_LARB_19_BASE	(IO_PHYS + 0x0a010000)
    138. 

  138. #define SMI_LARB_21_BASE	(IO_PHYS + 0x0802e000)
    139. 

  139. #define SMI_LARB_23_BASE	(IO_PHYS + 0x0800d000)
    140. 

  140. #define SMI_LARB_27_BASE	(IO_PHYS + 0x07201000)
    141. 

  141. #define SMI_LARB_28_BASE	(IO_PHYS + 0x00000000)
    142. 

  142. #define SMI_LARB_REG_RNG_SIZE	(0x1000)
    143. 

  143. 

  144. /*******************************************************************************
    145. 

  145.  * APMIXEDSYS related constants
    146. 

  146.  ******************************************************************************/
    147. 

  147. #define APMIXEDSYS		(IO_PHYS + 0x0000C000)
    148. 

  148. 

  149. /*******************************************************************************
    150. 

  150.  * VPPSYS related constants
    151. 

  151.  ******************************************************************************/
    152. 

  152. #define VPPSYS0_BASE		(IO_PHYS + 0x04000000)
    153. 

  153. #define VPPSYS1_BASE		(IO_PHYS + 0x04f00000)
    154. 

  154. 

  155. /*******************************************************************************
    156. 

  156.  * VDOSYS related constants
    157. 

  157.  ******************************************************************************/
    158. 

  158. #define VDOSYS0_BASE		(IO_PHYS + 0x0C01D000)
    159. 

  159. #define VDOSYS1_BASE		(IO_PHYS + 0x0C100000)
    160. 

  160. 

  161. /*******************************************************************************
    162. 

  162.  * DP related constants
    163. 

  163.  ******************************************************************************/
    164. 

  164. #define EDP_SEC_BASE		(IO_PHYS + 0x2EC50000)
    165. 

  165. #define DP_SEC_BASE		(IO_PHYS + 0x2EC10000)
    166. 

  166. #define EDP_SEC_SIZE		(0x1000)
    167. 

  167. #define DP_SEC_SIZE		(0x1000)
    168. 

  168. 

  169. /*******************************************************************************
    170. 

  170.  * EMI MPU related constants
    171. 

  171.  *******************************************************************************/
    172. 

  172. #define EMI_MPU_BASE		(IO_PHYS + 0x00428000)
    173. 

  173. #define SUB_EMI_MPU_BASE	(IO_PHYS + 0x00528000)
    174. 

  174. 

  175. /*******************************************************************************
    176. 

  176.  * System counter frequency related constants
    177. 

  177.  ******************************************************************************/
    178. 

  178. #define SYS_COUNTER_FREQ_IN_HZ	(13000000)
    179. 

  179. #define SYS_COUNTER_FREQ_IN_MHZ	(13)
    180. 

  180. 

  181. /*******************************************************************************
    182. 

  182.  * Generic platform constants
    183. 

  183.  ******************************************************************************/
    184. 

  184. #define PLATFORM_STACK_SIZE		(0x800)
    185. 

  185. #define SOC_CHIP_ID			U(0x8196)
    186. 

  186. 

  187. /*******************************************************************************
    188. 

  188.  * Platform memory map related constants
    189. 

  189.  ******************************************************************************/
    190. 

  190. #define TZRAM_BASE			(0x94600000)
    191. 

  191. #define TZRAM_SIZE			(0x00200000)
    192. 

  192. 

  193. /*******************************************************************************
    194. 

  194.  * BL31 specific defines.
    195. 

  195.  ******************************************************************************/
    196. 

  196. /*
    197. 

  197.  * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
    198. 

  198.  * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
    199. 

  199.  * little space for growth.
    200. 

  200.  */
    201. 

  201. #define BL31_BASE			(TZRAM_BASE + 0x1000)
    202. 

  202. #define BL31_LIMIT			(TZRAM_BASE + TZRAM_SIZE)
    203. 

  203. 

  204. /*******************************************************************************
    205. 

  205.  * Platform specific page table and MMU setup constants
    206. 

  206.  ******************************************************************************/
    207. 

  207. #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 39)
    208. 

  208. #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 39)
    209. 

  209. #define MAX_XLAT_TABLES			(128)
    210. 

  210. #define MAX_MMAP_REGIONS		(512)
    211. 

  211. 

  212. /*******************************************************************************
    213. 

  213.  * CPU PM definitions
    214. 

  214.  *******************************************************************************/
    215. 

  215. #define PLAT_CPU_PM_B_BUCK_ISO_ID	(6)
    216. 

  216. #define PLAT_CPU_PM_ILDO_ID		(6)
    217. 

  217. #define CPU_IDLE_SRAM_BASE		(0x11B000)
    218. 

  218. #define CPU_IDLE_SRAM_SIZE		(0x1000)
    219. 

  219. 

  220. /*******************************************************************************
    221. 

  221.  * SYSTIMER related definitions
    222. 

  222.  ******************************************************************************/
    223. 

  223. #define SYSTIMER_BASE		(0x1C400000)
    224. 

  224. 

  225. #endif /* PLATFORM_DEF_H */
    226.