bl2_el3.ld.S 5.1 KB

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  1. /*
  2. * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <common/bl_common.ld.h>
  7. #include <lib/xlat_tables/xlat_tables_defs.h>
  8. OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
  9. OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
  10. ENTRY(bl2_entrypoint)
  11. MEMORY {
  12. #if BL2_IN_XIP_MEM
  13. ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE
  14. RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
  15. #else /* BL2_IN_XIP_MEM */
  16. RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
  17. #endif /* BL2_IN_XIP_MEM */
  18. #if SEPARATE_BL2_NOLOAD_REGION
  19. RAM_NOLOAD (rw!a): ORIGIN = BL2_NOLOAD_START, LENGTH = BL2_NOLOAD_LIMIT - BL2_NOLOAD_START
  20. #else /* SEPARATE_BL2_NOLOAD_REGION */
  21. # define RAM_NOLOAD RAM
  22. #endif /* SEPARATE_BL2_NOLOAD_REGION */
  23. }
  24. #if !BL2_IN_XIP_MEM
  25. # define ROM RAM
  26. #endif /* !BL2_IN_XIP_MEM */
  27. SECTIONS {
  28. #if BL2_IN_XIP_MEM
  29. . = BL2_RO_BASE;
  30. ASSERT(. == ALIGN(PAGE_SIZE),
  31. "BL2_RO_BASE address is not aligned on a page boundary.")
  32. #else /* BL2_IN_XIP_MEM */
  33. . = BL2_BASE;
  34. ASSERT(. == ALIGN(PAGE_SIZE),
  35. "BL2_BASE address is not aligned on a page boundary.")
  36. #endif /* BL2_IN_XIP_MEM */
  37. #if SEPARATE_CODE_AND_RODATA
  38. .text . : {
  39. __TEXT_START__ = .;
  40. __TEXT_RESIDENT_START__ = .;
  41. *bl2_el3_entrypoint.o(.text*)
  42. *(.text.asm.*)
  43. __TEXT_RESIDENT_END__ = .;
  44. *(SORT_BY_ALIGNMENT(.text*))
  45. *(.vectors)
  46. . = ALIGN(PAGE_SIZE);
  47. __TEXT_END__ = .;
  48. } >ROM
  49. .rodata . : {
  50. __RODATA_START__ = .;
  51. *(SORT_BY_ALIGNMENT(.rodata*))
  52. RODATA_COMMON
  53. . = ALIGN(PAGE_SIZE);
  54. __RODATA_END__ = .;
  55. } >ROM
  56. ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE,
  57. "Resident part of BL2 has exceeded its limit.")
  58. #else /* SEPARATE_CODE_AND_RODATA */
  59. ro . : {
  60. __RO_START__ = .;
  61. __TEXT_RESIDENT_START__ = .;
  62. *bl2_el3_entrypoint.o(.text*)
  63. *(.text.asm.*)
  64. __TEXT_RESIDENT_END__ = .;
  65. *(SORT_BY_ALIGNMENT(.text*))
  66. *(SORT_BY_ALIGNMENT(.rodata*))
  67. RODATA_COMMON
  68. *(.vectors)
  69. __RO_END_UNALIGNED__ = .;
  70. /*
  71. * Memory page(s) mapped to this section will be marked as read-only,
  72. * executable. No RW data from the next section must creep in. Ensure
  73. * that the rest of the current memory page is unused.
  74. */
  75. . = ALIGN(PAGE_SIZE);
  76. __RO_END__ = .;
  77. } >ROM
  78. #endif /* SEPARATE_CODE_AND_RODATA */
  79. ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
  80. "cpu_ops not defined for this platform.")
  81. #if BL2_IN_XIP_MEM
  82. . = BL2_RW_BASE;
  83. ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE),
  84. "BL2_RW_BASE address is not aligned on a page boundary.")
  85. #endif /* BL2_IN_XIP_MEM */
  86. __RW_START__ = .;
  87. DATA_SECTION >RAM AT>ROM
  88. __DATA_RAM_START__ = __DATA_START__;
  89. __DATA_RAM_END__ = __DATA_END__;
  90. RELA_SECTION >RAM
  91. #if SEPARATE_BL2_NOLOAD_REGION
  92. SAVED_ADDR = .;
  93. . = BL2_NOLOAD_START;
  94. __BL2_NOLOAD_START__ = .;
  95. #endif /* SEPARATE_BL2_NOLOAD_REGION */
  96. STACK_SECTION >RAM_NOLOAD
  97. BSS_SECTION >RAM_NOLOAD
  98. XLAT_TABLE_SECTION >RAM_NOLOAD
  99. #if SEPARATE_BL2_NOLOAD_REGION
  100. __BL2_NOLOAD_END__ = .;
  101. . = SAVED_ADDR;
  102. #endif /* SEPARATE_BL2_NOLOAD_REGION */
  103. #if USE_COHERENT_MEM
  104. /*
  105. * The base address of the coherent memory section must be page-aligned to
  106. * guarantee that the coherent data are stored on their own pages and are
  107. * not mixed with normal data. This is required to set up the correct
  108. * memory attributes for the coherent data page tables.
  109. */
  110. coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
  111. __COHERENT_RAM_START__ = .;
  112. *(tzfw_coherent_mem)
  113. __COHERENT_RAM_END_UNALIGNED__ = .;
  114. /*
  115. * Memory page(s) mapped to this section will be marked as device
  116. * memory. No other unexpected data must creep in. Ensure the rest of
  117. * the current memory page is unused.
  118. */
  119. . = ALIGN(PAGE_SIZE);
  120. __COHERENT_RAM_END__ = .;
  121. } >RAM
  122. #endif /* USE_COHERENT_MEM */
  123. __RW_END__ = .;
  124. __BL2_END__ = .;
  125. /DISCARD/ : {
  126. *(.dynsym .dynstr .hash .gnu.hash)
  127. }
  128. #if BL2_IN_XIP_MEM
  129. __BL2_RAM_START__ = ADDR(.data);
  130. __BL2_RAM_END__ = .;
  131. __DATA_ROM_START__ = LOADADDR(.data);
  132. __DATA_SIZE__ = SIZEOF(.data);
  133. /*
  134. * The .data section is the last PROGBITS section so its end marks the end
  135. * of BL2's RO content in XIP memory.
  136. */
  137. __BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
  138. ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT,
  139. "BL2's RO content has exceeded its limit.")
  140. #endif /* BL2_IN_XIP_MEM */
  141. __BSS_SIZE__ = SIZEOF(.bss);
  142. #if USE_COHERENT_MEM
  143. __COHERENT_RAM_UNALIGNED_SIZE__ =
  144. __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
  145. #endif /* USE_COHERENT_MEM */
  146. #if BL2_IN_XIP_MEM
  147. ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.")
  148. #else /* BL2_IN_XIP_MEM */
  149. ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
  150. #endif /* BL2_IN_XIP_MEM */
  151. }