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plat
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mediatek
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drivers
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dfd
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mt8188
/
plat_dfd.h

plat_dfd.h 2.8 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2022, MediaTek Inc. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef PLAT_DFD_H
    8. 

  8. #define PLAT_DFD_H
    9. 

  9. 

  10. #include <lib/mmio.h>
    11. 

  11. #include <platform_def.h>
    12. 

  12. 

  13. #define sync_writel(addr, val) do { mmio_write_32((addr), (val)); dsbsy(); } while (0)
    14. 

  14. 

  15. #define PLAT_MTK_DFD_SETUP_MAGIC		(0x99716150)
    16. 

  16. #define PLAT_MTK_DFD_READ_MAGIC			(0x99716151)
    17. 

  17. #define PLAT_MTK_DFD_WRITE_MAGIC		(0x99716152)
    18. 

  18. 

  19. #define MTK_DRM_LATCH_CTL1			(DRM_BASE + 0x40)
    20. 

  20. #define MTK_DRM_LATCH_CTL2			(DRM_BASE + 0x44)
    21. 

  21. 

  22. #define MTK_WDT_BASE				(RGU_BASE)
    23. 

  23. #define MTK_WDT_INTERVAL			(MTK_WDT_BASE + 0x10)
    24. 

  24. #define MTK_WDT_LATCH_CTL2			(MTK_WDT_BASE + 0x48)
    25. 

  25. 

  26. #define MCU_BIU_BASE				(MCUCFG_BASE)
    27. 

  27. #define MISC1_CFG_BASE				(MCU_BIU_BASE + 0xE040)
    28. 

  28. #define DFD_INTERNAL_CTL			(MISC1_CFG_BASE + 0x00)
    29. 

  29. #define DFD_INTERNAL_PWR_ON			(MISC1_CFG_BASE + 0x08)
    30. 

  30. #define DFD_CHAIN_LENGTH0			(MISC1_CFG_BASE + 0x0C)
    31. 

  31. #define DFD_INTERNAL_SHIFT_CLK_RATIO		(MISC1_CFG_BASE + 0x10)
    32. 

  32. #define DFD_CHAIN_LENGTH1			(MISC1_CFG_BASE + 0x1C)
    33. 

  33. #define DFD_CHAIN_LENGTH2			(MISC1_CFG_BASE + 0x20)
    34. 

  34. #define DFD_CHAIN_LENGTH3			(MISC1_CFG_BASE + 0x24)
    35. 

  35. #define DFD_INTERNAL_TEST_SO_0			(MISC1_CFG_BASE + 0x28)
    36. 

  36. #define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP	(MISC1_CFG_BASE + 0x30)
    37. 

  37. #define DFD_INTERNAL_TEST_SO_OVER_64		(MISC1_CFG_BASE + 0x34)
    38. 

  38. #define DFD_INTERNAL_SW_NS_TRIGGER		(MISC1_CFG_BASE + 0x3c)
    39. 

  39. #define DFD_V30_CTL				(MISC1_CFG_BASE + 0x48)
    40. 

  40. #define DFD_V30_BASE_ADDR			(MISC1_CFG_BASE + 0x4C)
    41. 

  41. #define DFD_POWER_CTL				(MISC1_CFG_BASE + 0x50)
    42. 

  42. #define DFD_TEST_SI_0				(MISC1_CFG_BASE + 0x58)
    43. 

  43. #define DFD_TEST_SI_1				(MISC1_CFG_BASE + 0x5C)
    44. 

  44. #define DFD_CLEAN_STATUS			(MISC1_CFG_BASE + 0x60)
    45. 

  45. #define DFD_TEST_SI_2				(MISC1_CFG_BASE + 0x1D8)
    46. 

  46. #define DFD_TEST_SI_3				(MISC1_CFG_BASE + 0x1DC)
    47. 

  47. #define DFD_READ_ADDR				(MISC1_CFG_BASE + 0x1E8)
    48. 

  48. #define DFD_HW_TRIGGER_MASK			(MISC1_CFG_BASE + 0xBC)
    49. 

  49. 

  50. #define DFD_V35_ENABLE				(MCU_BIU_BASE + 0xE0A8)
    51. 

  51. #define DFD_V35_TAP_NUMBER			(MCU_BIU_BASE + 0xE0AC)
    52. 

  52. #define DFD_V35_TAP_EN				(MCU_BIU_BASE + 0xE0B0)
    53. 

  53. #define DFD_V35_CTL				(MCU_BIU_BASE + 0xE0B4)
    54. 

  54. #define DFD_V35_SEQ0_0				(MCU_BIU_BASE + 0xE0C0)
    55. 

  55. #define DFD_V35_SEQ0_1				(MCU_BIU_BASE + 0xE0C4)
    56. 

  56. #define DFD_V50_GROUP_0_63_DIFF			(MCU_BIU_BASE + 0xE2AC)
    57. 

  57. 

  58. #define DFD_O_PROTECT_EN_REG			(0x10001220)
    59. 

  59. #define DFD_O_INTRF_MCU_PWR_CTL_MASK		(0x10001A3C)
    60. 

  60. #define DFD_O_SET_BASEADDR_REG			(0x10043000)
    61. 

  61. #define DFD_O_REG_0				(0x10001390)
    62. 

  62. 

  63. #define DFD_CACHE_DUMP_ENABLE			(1U)
    64. 

  64. #define DFD_PARITY_ERR_TRIGGER			(2U)
    65. 

  65. 

  66. #define DFD_V35_TAP_EN_VAL			(0x43FF)
    67. 

  67. #define DFD_V35_SEQ0_0_VAL			(0x63668820)
    68. 

  68. #define DFD_READ_ADDR_VAL			(0x40000008)
    69. 

  69. #define DFD_CHAIN_LENGTH_VAL			(0xFFFFFFFF)
    70. 

  70. 

  71. #define MTK_WDT_LATCH_CTL2_VAL			(0x9507FFFF)
    72. 

  72. #define MTK_WDT_INTERVAL_VAL			(0x6600000A)
    73. 

  73. #define MTK_DRM_LATCH_CTL2_VAL			(0x950607D0)
    74. 

  74. #define MTK_DRM_LATCH_CTL2_CACHE_VAL		(0x95065DC0)
    75. 

  75. 

  76. #define MTK_DRM_LATCH_CTL1_VAL			(0x95000013)
    77. 

  77. 

  78. #endif /* PLAT_DFD_H */
    79.