stm32mp157c-odyssey-som.dtsi 6.0 KB

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  1. /*
  2. * Copyright (C) 2019, STMicroelectronics. All Rights Reserved.
  3. * Copyright (C) 2021, Grzegorz Szymaszek.
  4. *
  5. * SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
  6. */
  7. #include "stm32mp157.dtsi"
  8. #include "stm32mp15xc.dtsi"
  9. #include "stm32mp15-pinctrl.dtsi"
  10. #include "stm32mp15xxac-pinctrl.dtsi"
  11. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  12. #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
  13. / {
  14. memory@c0000000 {
  15. device_type = "memory";
  16. reg = <0xc0000000 0x20000000>;
  17. };
  18. vin: vin {
  19. compatible = "regulator-fixed";
  20. regulator-name = "vin";
  21. regulator-min-microvolt = <5000000>;
  22. regulator-max-microvolt = <5000000>;
  23. regulator-always-on;
  24. };
  25. };
  26. &bsec {
  27. board_id: board_id@ec {
  28. reg = <0xec 0x4>;
  29. st,non-secure-otp;
  30. };
  31. };
  32. &clk_hse {
  33. st,digbypass;
  34. };
  35. &cpu0 {
  36. cpu-supply = <&vddcore>;
  37. };
  38. &cpu1 {
  39. cpu-supply = <&vddcore>;
  40. };
  41. &cryp1 {
  42. status = "okay";
  43. };
  44. &hash1 {
  45. status = "okay";
  46. };
  47. &i2c2 {
  48. pinctrl-names = "default";
  49. pinctrl-0 = <&i2c2_pins_a>;
  50. clock-frequency = <400000>;
  51. i2c-scl-rising-time-ns = <185>;
  52. i2c-scl-falling-time-ns = <20>;
  53. status = "okay";
  54. pmic: stpmic@33 {
  55. compatible = "st,stpmic1";
  56. reg = <0x33>;
  57. interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
  58. interrupt-controller;
  59. #interrupt-cells = <2>;
  60. status = "okay";
  61. regulators {
  62. compatible = "st,stpmic1-regulators";
  63. buck1-supply = <&vin>;
  64. buck2-supply = <&vin>;
  65. buck3-supply = <&vin>;
  66. buck4-supply = <&vin>;
  67. ldo1-supply = <&v3v3>;
  68. ldo2-supply = <&vin>;
  69. ldo3-supply = <&vdd_ddr>;
  70. ldo4-supply = <&vin>;
  71. ldo5-supply = <&vin>;
  72. ldo6-supply = <&v3v3>;
  73. vref_ddr-supply = <&vin>;
  74. boost-supply = <&vin>;
  75. pwr_sw1-supply = <&bst_out>;
  76. pwr_sw2-supply = <&bst_out>;
  77. vddcore: buck1 {
  78. regulator-name = "vddcore";
  79. regulator-min-microvolt = <1200000>;
  80. regulator-max-microvolt = <1350000>;
  81. regulator-always-on;
  82. regulator-initial-mode = <0>;
  83. regulator-over-current-protection;
  84. };
  85. vdd_ddr: buck2 {
  86. regulator-name = "vdd_ddr";
  87. regulator-min-microvolt = <1350000>;
  88. regulator-max-microvolt = <1350000>;
  89. regulator-always-on;
  90. regulator-initial-mode = <0>;
  91. regulator-over-current-protection;
  92. };
  93. vdd: buck3 {
  94. regulator-name = "vdd";
  95. regulator-min-microvolt = <3300000>;
  96. regulator-max-microvolt = <3300000>;
  97. regulator-always-on;
  98. st,mask-reset;
  99. regulator-initial-mode = <0>;
  100. regulator-over-current-protection;
  101. };
  102. v3v3: buck4 {
  103. regulator-name = "v3v3";
  104. regulator-min-microvolt = <3300000>;
  105. regulator-max-microvolt = <3300000>;
  106. regulator-always-on;
  107. regulator-over-current-protection;
  108. regulator-initial-mode = <0>;
  109. };
  110. v1v8_audio: ldo1 {
  111. regulator-name = "v1v8_audio";
  112. regulator-min-microvolt = <1800000>;
  113. regulator-max-microvolt = <1800000>;
  114. regulator-always-on;
  115. };
  116. v3v3_hdmi: ldo2 {
  117. regulator-name = "v3v3_hdmi";
  118. regulator-min-microvolt = <3300000>;
  119. regulator-max-microvolt = <3300000>;
  120. regulator-always-on;
  121. };
  122. vtt_ddr: ldo3 {
  123. regulator-name = "vtt_ddr";
  124. regulator-always-on;
  125. regulator-over-current-protection;
  126. st,regulator-sink-source;
  127. };
  128. vdd_usb: ldo4 {
  129. regulator-name = "vdd_usb";
  130. regulator-min-microvolt = <3300000>;
  131. regulator-max-microvolt = <3300000>;
  132. regulator-always-on;
  133. };
  134. vdda: ldo5 {
  135. regulator-name = "vdda";
  136. regulator-min-microvolt = <2900000>;
  137. regulator-max-microvolt = <2900000>;
  138. regulator-boot-on;
  139. };
  140. v1v2_hdmi: ldo6 {
  141. regulator-name = "v1v2_hdmi";
  142. regulator-min-microvolt = <1200000>;
  143. regulator-max-microvolt = <1200000>;
  144. regulator-always-on;
  145. };
  146. vref_ddr: vref_ddr {
  147. regulator-name = "vref_ddr";
  148. regulator-always-on;
  149. };
  150. bst_out: boost {
  151. regulator-name = "bst_out";
  152. };
  153. vbus_otg: pwr_sw1 {
  154. regulator-name = "vbus_otg";
  155. };
  156. vbus_sw: pwr_sw2 {
  157. regulator-name = "vbus_sw";
  158. regulator-active-discharge = <1>;
  159. };
  160. };
  161. pmic_watchdog: watchdog {
  162. compatible = "st,stpmic1-wdt";
  163. status = "disabled";
  164. };
  165. };
  166. };
  167. &iwdg2 {
  168. timeout-sec = <32>;
  169. status = "okay";
  170. };
  171. &pwr_regulators {
  172. vdd-supply = <&vdd>;
  173. vdd_3v3_usbfs-supply = <&vdd_usb>;
  174. };
  175. &rcc {
  176. st,clksrc = <
  177. CLK_MPU_PLL1P
  178. CLK_AXI_PLL2P
  179. CLK_MCU_PLL3P
  180. CLK_PLL12_HSE
  181. CLK_PLL3_HSE
  182. CLK_PLL4_HSE
  183. CLK_RTC_LSE
  184. CLK_MCO1_DISABLED
  185. CLK_MCO2_DISABLED
  186. >;
  187. st,clkdiv = <
  188. 1 /*MPU*/
  189. 0 /*AXI*/
  190. 0 /*MCU*/
  191. 1 /*APB1*/
  192. 1 /*APB2*/
  193. 1 /*APB3*/
  194. 1 /*APB4*/
  195. 2 /*APB5*/
  196. 23 /*RTC*/
  197. 0 /*MCO1*/
  198. 0 /*MCO2*/
  199. >;
  200. st,pkcs = <
  201. CLK_CKPER_HSE
  202. CLK_FMC_ACLK
  203. CLK_QSPI_ACLK
  204. CLK_ETH_PLL4P
  205. CLK_SDMMC12_PLL4P
  206. CLK_DSI_DSIPLL
  207. CLK_STGEN_HSE
  208. CLK_USBPHY_HSE
  209. CLK_SPI2S1_PLL3Q
  210. CLK_SPI2S23_PLL3Q
  211. CLK_SPI45_HSI
  212. CLK_SPI6_HSI
  213. CLK_I2C46_HSI
  214. CLK_SDMMC3_PLL4P
  215. CLK_USBO_USBPHY
  216. CLK_ADC_CKPER
  217. CLK_CEC_LSE
  218. CLK_I2C12_HSI
  219. CLK_I2C35_HSI
  220. CLK_UART1_HSI
  221. CLK_UART24_HSI
  222. CLK_UART35_HSI
  223. CLK_UART6_HSI
  224. CLK_UART78_HSI
  225. CLK_SPDIF_PLL4P
  226. CLK_FDCAN_PLL4R
  227. CLK_SAI1_PLL3Q
  228. CLK_SAI2_PLL3Q
  229. CLK_SAI3_PLL3Q
  230. CLK_SAI4_PLL3Q
  231. CLK_RNG1_LSI
  232. CLK_RNG2_LSI
  233. CLK_LPTIM1_PCLK1
  234. CLK_LPTIM23_PCLK3
  235. CLK_LPTIM45_LSE
  236. >;
  237. /* VCO = 1300.0 MHz => P = 650 (CPU) */
  238. pll1: st,pll@0 {
  239. compatible = "st,stm32mp1-pll";
  240. reg = <0>;
  241. cfg = <2 80 0 0 0 PQR(1,0,0)>;
  242. frac = <0x800>;
  243. };
  244. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  245. pll2: st,pll@1 {
  246. compatible = "st,stm32mp1-pll";
  247. reg = <1>;
  248. cfg = <2 65 1 0 0 PQR(1,1,1)>;
  249. frac = <0x1400>;
  250. };
  251. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  252. pll3: st,pll@2 {
  253. compatible = "st,stm32mp1-pll";
  254. reg = <2>;
  255. cfg = <1 33 1 16 36 PQR(1,1,1)>;
  256. frac = <0x1a04>;
  257. };
  258. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  259. pll4: st,pll@3 {
  260. compatible = "st,stm32mp1-pll";
  261. reg = <3>;
  262. cfg = <3 98 5 7 7 PQR(1,1,1)>;
  263. };
  264. };
  265. &rng1 {
  266. status = "okay";
  267. };
  268. &rtc {
  269. status = "okay";
  270. };
  271. &sdmmc2 {
  272. pinctrl-names = "default";
  273. pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>;
  274. non-removable;
  275. no-sd;
  276. no-sdio;
  277. st,neg-edge;
  278. bus-width = <8>;
  279. vmmc-supply = <&v3v3>;
  280. vqmmc-supply = <&vdd>;
  281. mmc-ddr-3_3v;
  282. status = "okay";
  283. };