stm32mp15-ddr.dtsi 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. / {
  6. soc {
  7. ddr: ddr@5a003000{
  8. compatible = "st,stm32mp1-ddr";
  9. reg = <0x5A003000 0x550
  10. 0x5A004000 0x234>;
  11. clocks = <&rcc AXIDCG>,
  12. <&rcc DDRC1>,
  13. <&rcc DDRC2>,
  14. <&rcc DDRPHYC>,
  15. <&rcc DDRCAPB>,
  16. <&rcc DDRPHYCAPB>;
  17. clock-names = "axidcg",
  18. "ddrc1",
  19. "ddrc2",
  20. "ddrphyc",
  21. "ddrcapb",
  22. "ddrphycapb";
  23. st,mem-name = DDR_MEM_NAME;
  24. st,mem-speed = <DDR_MEM_SPEED>;
  25. st,mem-size = <DDR_MEM_SIZE>;
  26. st,ctl-reg = <
  27. DDR_MSTR
  28. DDR_MRCTRL0
  29. DDR_MRCTRL1
  30. DDR_DERATEEN
  31. DDR_DERATEINT
  32. DDR_PWRCTL
  33. DDR_PWRTMG
  34. DDR_HWLPCTL
  35. DDR_RFSHCTL0
  36. DDR_RFSHCTL3
  37. DDR_CRCPARCTL0
  38. DDR_ZQCTL0
  39. DDR_DFITMG0
  40. DDR_DFITMG1
  41. DDR_DFILPCFG0
  42. DDR_DFIUPD0
  43. DDR_DFIUPD1
  44. DDR_DFIUPD2
  45. DDR_DFIPHYMSTR
  46. DDR_ODTMAP
  47. DDR_DBG0
  48. DDR_DBG1
  49. DDR_DBGCMD
  50. DDR_POISONCFG
  51. DDR_PCCFG
  52. >;
  53. st,ctl-timing = <
  54. DDR_RFSHTMG
  55. DDR_DRAMTMG0
  56. DDR_DRAMTMG1
  57. DDR_DRAMTMG2
  58. DDR_DRAMTMG3
  59. DDR_DRAMTMG4
  60. DDR_DRAMTMG5
  61. DDR_DRAMTMG6
  62. DDR_DRAMTMG7
  63. DDR_DRAMTMG8
  64. DDR_DRAMTMG14
  65. DDR_ODTCFG
  66. >;
  67. st,ctl-map = <
  68. DDR_ADDRMAP1
  69. DDR_ADDRMAP2
  70. DDR_ADDRMAP3
  71. DDR_ADDRMAP4
  72. DDR_ADDRMAP5
  73. DDR_ADDRMAP6
  74. DDR_ADDRMAP9
  75. DDR_ADDRMAP10
  76. DDR_ADDRMAP11
  77. >;
  78. st,ctl-perf = <
  79. DDR_SCHED
  80. DDR_SCHED1
  81. DDR_PERFHPR1
  82. DDR_PERFLPR1
  83. DDR_PERFWR1
  84. DDR_PCFGR_0
  85. DDR_PCFGW_0
  86. DDR_PCFGQOS0_0
  87. DDR_PCFGQOS1_0
  88. DDR_PCFGWQOS0_0
  89. DDR_PCFGWQOS1_0
  90. DDR_PCFGR_1
  91. DDR_PCFGW_1
  92. DDR_PCFGQOS0_1
  93. DDR_PCFGQOS1_1
  94. DDR_PCFGWQOS0_1
  95. DDR_PCFGWQOS1_1
  96. >;
  97. st,phy-reg = <
  98. DDR_PGCR
  99. DDR_ACIOCR
  100. DDR_DXCCR
  101. DDR_DSGCR
  102. DDR_DCR
  103. DDR_ODTCR
  104. DDR_ZQ0CR1
  105. DDR_DX0GCR
  106. DDR_DX1GCR
  107. DDR_DX2GCR
  108. DDR_DX3GCR
  109. >;
  110. st,phy-timing = <
  111. DDR_PTR0
  112. DDR_PTR1
  113. DDR_PTR2
  114. DDR_DTPR0
  115. DDR_DTPR1
  116. DDR_DTPR2
  117. DDR_MR0
  118. DDR_MR1
  119. DDR_MR2
  120. DDR_MR3
  121. >;
  122. st,phy-cal = <
  123. DDR_DX0DLLCR
  124. DDR_DX0DQTR
  125. DDR_DX0DQSTR
  126. DDR_DX1DLLCR
  127. DDR_DX1DQTR
  128. DDR_DX1DQSTR
  129. DDR_DX2DLLCR
  130. DDR_DX2DQTR
  131. DDR_DX2DQSTR
  132. DDR_DX3DLLCR
  133. DDR_DX3DQTR
  134. DDR_DX3DQSTR
  135. >;
  136. status = "okay";
  137. };
  138. };
  139. };