stm32mp157c-ed1.dts 6.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
  4. * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
  5. */
  6. /dts-v1/;
  7. #include "stm32mp157.dtsi"
  8. #include "stm32mp15xc.dtsi"
  9. #include "stm32mp15-pinctrl.dtsi"
  10. #include "stm32mp15xxaa-pinctrl.dtsi"
  11. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  12. #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  13. / {
  14. model = "STMicroelectronics STM32MP157C eval daughter";
  15. compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. memory@c0000000 {
  20. device_type = "memory";
  21. reg = <0xC0000000 0x40000000>;
  22. };
  23. aliases {
  24. serial0 = &uart4;
  25. };
  26. };
  27. &bsec {
  28. board_id: board_id@ec {
  29. reg = <0xec 0x4>;
  30. status = "okay";
  31. secure-status = "okay";
  32. };
  33. };
  34. &clk_hse {
  35. st,digbypass;
  36. };
  37. &cpu0 {
  38. cpu-supply = <&vddcore>;
  39. };
  40. &cpu1 {
  41. cpu-supply = <&vddcore>;
  42. };
  43. &cryp1 {
  44. status="okay";
  45. };
  46. &hash1 {
  47. status = "okay";
  48. };
  49. &i2c4 {
  50. pinctrl-names = "default";
  51. pinctrl-0 = <&i2c4_pins_a>;
  52. i2c-scl-rising-time-ns = <185>;
  53. i2c-scl-falling-time-ns = <20>;
  54. clock-frequency = <400000>;
  55. status = "okay";
  56. pmic: stpmic@33 {
  57. compatible = "st,stpmic1";
  58. reg = <0x33>;
  59. interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
  60. interrupt-controller;
  61. #interrupt-cells = <2>;
  62. status = "okay";
  63. regulators {
  64. compatible = "st,stpmic1-regulators";
  65. ldo1-supply = <&v3v3>;
  66. ldo2-supply = <&v3v3>;
  67. ldo3-supply = <&vdd_ddr>;
  68. ldo5-supply = <&v3v3>;
  69. ldo6-supply = <&v3v3>;
  70. pwr_sw1-supply = <&bst_out>;
  71. pwr_sw2-supply = <&bst_out>;
  72. vddcore: buck1 {
  73. regulator-name = "vddcore";
  74. regulator-min-microvolt = <1200000>;
  75. regulator-max-microvolt = <1350000>;
  76. regulator-always-on;
  77. regulator-initial-mode = <0>;
  78. regulator-over-current-protection;
  79. };
  80. vdd_ddr: buck2 {
  81. regulator-name = "vdd_ddr";
  82. regulator-min-microvolt = <1350000>;
  83. regulator-max-microvolt = <1350000>;
  84. regulator-always-on;
  85. regulator-initial-mode = <0>;
  86. regulator-over-current-protection;
  87. };
  88. vdd: buck3 {
  89. regulator-name = "vdd";
  90. regulator-min-microvolt = <3300000>;
  91. regulator-max-microvolt = <3300000>;
  92. regulator-always-on;
  93. st,mask-reset;
  94. regulator-initial-mode = <0>;
  95. regulator-over-current-protection;
  96. };
  97. v3v3: buck4 {
  98. regulator-name = "v3v3";
  99. regulator-min-microvolt = <3300000>;
  100. regulator-max-microvolt = <3300000>;
  101. regulator-always-on;
  102. regulator-over-current-protection;
  103. regulator-initial-mode = <0>;
  104. };
  105. vdda: ldo1 {
  106. regulator-name = "vdda";
  107. regulator-min-microvolt = <2900000>;
  108. regulator-max-microvolt = <2900000>;
  109. };
  110. v2v8: ldo2 {
  111. regulator-name = "v2v8";
  112. regulator-min-microvolt = <2800000>;
  113. regulator-max-microvolt = <2800000>;
  114. };
  115. vtt_ddr: ldo3 {
  116. regulator-name = "vtt_ddr";
  117. regulator-min-microvolt = <500000>;
  118. regulator-max-microvolt = <750000>;
  119. regulator-always-on;
  120. regulator-over-current-protection;
  121. };
  122. vdd_usb: ldo4 {
  123. regulator-name = "vdd_usb";
  124. };
  125. vdd_sd: ldo5 {
  126. regulator-name = "vdd_sd";
  127. regulator-min-microvolt = <2900000>;
  128. regulator-max-microvolt = <2900000>;
  129. regulator-boot-on;
  130. };
  131. v1v8: ldo6 {
  132. regulator-name = "v1v8";
  133. regulator-min-microvolt = <1800000>;
  134. regulator-max-microvolt = <1800000>;
  135. };
  136. vref_ddr: vref_ddr {
  137. regulator-name = "vref_ddr";
  138. regulator-always-on;
  139. };
  140. bst_out: boost {
  141. regulator-name = "bst_out";
  142. };
  143. vbus_otg: pwr_sw1 {
  144. regulator-name = "vbus_otg";
  145. };
  146. vbus_sw: pwr_sw2 {
  147. regulator-name = "vbus_sw";
  148. regulator-active-discharge = <1>;
  149. };
  150. };
  151. onkey {
  152. compatible = "st,stpmic1-onkey";
  153. power-off-time-sec = <10>;
  154. status = "okay";
  155. };
  156. watchdog {
  157. compatible = "st,stpmic1-wdt";
  158. status = "disabled";
  159. };
  160. };
  161. };
  162. &iwdg2 {
  163. timeout-sec = <32>;
  164. status = "okay";
  165. };
  166. &pwr_regulators {
  167. vdd-supply = <&vdd>;
  168. vdd_3v3_usbfs-supply = <&vdd_usb>;
  169. };
  170. &rcc {
  171. secure-status = "disabled";
  172. st,clksrc = <
  173. CLK_MPU_PLL1P
  174. CLK_AXI_PLL2P
  175. CLK_MCU_PLL3P
  176. CLK_PLL12_HSE
  177. CLK_PLL3_HSE
  178. CLK_PLL4_HSE
  179. CLK_RTC_LSE
  180. CLK_MCO1_DISABLED
  181. CLK_MCO2_DISABLED
  182. >;
  183. st,clkdiv = <
  184. 1 /*MPU*/
  185. 0 /*AXI*/
  186. 0 /*MCU*/
  187. 1 /*APB1*/
  188. 1 /*APB2*/
  189. 1 /*APB3*/
  190. 1 /*APB4*/
  191. 2 /*APB5*/
  192. 23 /*RTC*/
  193. 0 /*MCO1*/
  194. 0 /*MCO2*/
  195. >;
  196. st,pkcs = <
  197. CLK_CKPER_HSE
  198. CLK_FMC_ACLK
  199. CLK_QSPI_ACLK
  200. CLK_ETH_DISABLED
  201. CLK_SDMMC12_PLL4P
  202. CLK_DSI_DSIPLL
  203. CLK_STGEN_HSE
  204. CLK_USBPHY_HSE
  205. CLK_SPI2S1_PLL3Q
  206. CLK_SPI2S23_PLL3Q
  207. CLK_SPI45_HSI
  208. CLK_SPI6_HSI
  209. CLK_I2C46_HSI
  210. CLK_SDMMC3_PLL4P
  211. CLK_USBO_USBPHY
  212. CLK_ADC_CKPER
  213. CLK_CEC_LSE
  214. CLK_I2C12_HSI
  215. CLK_I2C35_HSI
  216. CLK_UART1_HSI
  217. CLK_UART24_HSI
  218. CLK_UART35_HSI
  219. CLK_UART6_HSI
  220. CLK_UART78_HSI
  221. CLK_SPDIF_PLL4P
  222. CLK_FDCAN_PLL4R
  223. CLK_SAI1_PLL3Q
  224. CLK_SAI2_PLL3Q
  225. CLK_SAI3_PLL3Q
  226. CLK_SAI4_PLL3Q
  227. CLK_RNG1_LSI
  228. CLK_RNG2_LSI
  229. CLK_LPTIM1_PCLK1
  230. CLK_LPTIM23_PCLK3
  231. CLK_LPTIM45_LSE
  232. >;
  233. /* VCO = 1300.0 MHz => P = 650 (CPU) */
  234. pll1: st,pll@0 {
  235. cfg = < 2 80 0 0 0 PQR(1,0,0) >;
  236. frac = < 0x800 >;
  237. };
  238. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  239. pll2: st,pll@1 {
  240. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  241. frac = < 0x1400 >;
  242. };
  243. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  244. pll3: st,pll@2 {
  245. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  246. frac = < 0x1a04 >;
  247. };
  248. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  249. pll4: st,pll@3 {
  250. cfg = < 3 98 5 7 7 PQR(1,1,1) >;
  251. };
  252. };
  253. &rng1 {
  254. status = "okay";
  255. };
  256. &rtc {
  257. status = "okay";
  258. };
  259. &sdmmc1 {
  260. pinctrl-names = "default";
  261. pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
  262. disable-wp;
  263. st,sig-dir;
  264. st,neg-edge;
  265. st,use-ckin;
  266. bus-width = <4>;
  267. vmmc-supply = <&vdd_sd>;
  268. sd-uhs-sdr12;
  269. sd-uhs-sdr25;
  270. sd-uhs-sdr50;
  271. sd-uhs-ddr50;
  272. status = "okay";
  273. };
  274. &sdmmc2 {
  275. pinctrl-names = "default";
  276. pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
  277. non-removable;
  278. no-sd;
  279. no-sdio;
  280. st,neg-edge;
  281. bus-width = <8>;
  282. vmmc-supply = <&v3v3>;
  283. vqmmc-supply = <&vdd>;
  284. mmc-ddr-3_3v;
  285. status = "okay";
  286. };
  287. &uart4 {
  288. pinctrl-names = "default";
  289. pinctrl-0 = <&uart4_pins_a>;
  290. status = "okay";
  291. };