mmc.h 7.9 KB

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  1. /*
  2. * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #ifndef MMC_H
  7. #define MMC_H
  8. #include <stdint.h>
  9. #include <lib/utils_def.h>
  10. #define MMC_BLOCK_SIZE U(512)
  11. #define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1))
  12. #define MMC_BOOT_CLK_RATE (400 * 1000)
  13. #define MMC_CMD(_x) U(_x)
  14. #define MMC_ACMD(_x) U(_x)
  15. #define OCR_POWERUP BIT(31)
  16. #define OCR_HCS BIT(30)
  17. #define OCR_BYTE_MODE (U(0) << 29)
  18. #define OCR_SECTOR_MODE (U(2) << 29)
  19. #define OCR_ACCESS_MODE_MASK (U(3) << 29)
  20. #define OCR_3_5_3_6 BIT(23)
  21. #define OCR_3_4_3_5 BIT(22)
  22. #define OCR_3_3_3_4 BIT(21)
  23. #define OCR_3_2_3_3 BIT(20)
  24. #define OCR_3_1_3_2 BIT(19)
  25. #define OCR_3_0_3_1 BIT(18)
  26. #define OCR_2_9_3_0 BIT(17)
  27. #define OCR_2_8_2_9 BIT(16)
  28. #define OCR_2_7_2_8 BIT(15)
  29. #define OCR_VDD_MIN_2V7 GENMASK(23, 15)
  30. #define OCR_VDD_MIN_2V0 GENMASK(14, 8)
  31. #define OCR_VDD_MIN_1V7 BIT(7)
  32. #define MMC_RSP_48 BIT(0)
  33. #define MMC_RSP_136 BIT(1) /* 136 bit response */
  34. #define MMC_RSP_CRC BIT(2) /* expect valid crc */
  35. #define MMC_RSP_CMD_IDX BIT(3) /* response contains cmd idx */
  36. #define MMC_RSP_BUSY BIT(4) /* device may be busy */
  37. /* JEDEC 4.51 chapter 6.12 */
  38. #define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC)
  39. #define MMC_RESPONSE_R1B (MMC_RESPONSE_R1 | MMC_RSP_BUSY)
  40. #define MMC_RESPONSE_R2 (MMC_RSP_48 | MMC_RSP_136 | MMC_RSP_CRC)
  41. #define MMC_RESPONSE_R3 (MMC_RSP_48)
  42. #define MMC_RESPONSE_R4 (MMC_RSP_48)
  43. #define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
  44. #define MMC_RESPONSE_R6 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
  45. #define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
  46. /* Value randomly chosen for eMMC RCA, it should be > 1 */
  47. #define MMC_FIX_RCA 6
  48. #define RCA_SHIFT_OFFSET 16
  49. #define CMD_EXTCSD_PARTITION_CONFIG 179
  50. #define CMD_EXTCSD_BUS_WIDTH 183
  51. #define CMD_EXTCSD_HS_TIMING 185
  52. #define CMD_EXTCSD_PART_SWITCH_TIME 199
  53. #define CMD_EXTCSD_SEC_CNT 212
  54. #define CMD_EXTCSD_BOOT_SIZE_MULT 226
  55. #define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0)
  56. #define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
  57. #define PART_CFG_BOOT_PARTITION1_ACCESS (U(1) << 0)
  58. #define PART_CFG_BOOT_PARTITION_NO_ACCESS U(0)
  59. #define PART_CFG_BOOT_PART_EN_MASK GENMASK(5, 3)
  60. #define PART_CFG_BOOT_PART_EN_SHIFT 3
  61. #define PART_CFG_CURRENT_BOOT_PARTITION(x) (((x) & PART_CFG_BOOT_PART_EN_MASK) >> \
  62. PART_CFG_BOOT_PART_EN_SHIFT)
  63. /* Values in EXT CSD register */
  64. #define MMC_BUS_WIDTH_1 U(0)
  65. #define MMC_BUS_WIDTH_4 U(1)
  66. #define MMC_BUS_WIDTH_8 U(2)
  67. #define MMC_BUS_WIDTH_DDR_4 U(5)
  68. #define MMC_BUS_WIDTH_DDR_8 U(6)
  69. #define MMC_BOOT_MODE_BACKWARD (U(0) << 3)
  70. #define MMC_BOOT_MODE_HS_TIMING (U(1) << 3)
  71. #define MMC_BOOT_MODE_DDR (U(2) << 3)
  72. #define EXTCSD_SET_CMD (U(0) << 24)
  73. #define EXTCSD_SET_BITS (U(1) << 24)
  74. #define EXTCSD_CLR_BITS (U(2) << 24)
  75. #define EXTCSD_WRITE_BYTES (U(3) << 24)
  76. #define EXTCSD_CMD(x) (((x) & 0xff) << 16)
  77. #define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
  78. #define EXTCSD_CMD_SET_NORMAL U(1)
  79. #define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
  80. #define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
  81. #define CSD_TRAN_SPEED_MULT_SHIFT 3
  82. #define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
  83. #define STATUS_READY_FOR_DATA BIT(8)
  84. #define STATUS_SWITCH_ERROR BIT(7)
  85. #define MMC_GET_STATE(x) (((x) >> 9) & 0xf)
  86. #define MMC_STATE_IDLE 0
  87. #define MMC_STATE_READY 1
  88. #define MMC_STATE_IDENT 2
  89. #define MMC_STATE_STBY 3
  90. #define MMC_STATE_TRAN 4
  91. #define MMC_STATE_DATA 5
  92. #define MMC_STATE_RCV 6
  93. #define MMC_STATE_PRG 7
  94. #define MMC_STATE_DIS 8
  95. #define MMC_STATE_BTST 9
  96. #define MMC_STATE_SLP 10
  97. #define MMC_FLAG_CMD23 (U(1) << 0)
  98. #define MMC_FLAG_SD_CMD6 (U(1) << 1)
  99. #define CMD8_CHECK_PATTERN U(0xAA)
  100. #define VHS_2_7_3_6_V BIT(8)
  101. #define SD_SCR_BUS_WIDTH_1 BIT(8)
  102. #define SD_SCR_BUS_WIDTH_4 BIT(10)
  103. #define SD_SWITCH_FUNC_CHECK 0U
  104. #define SD_SWITCH_FUNC_SWITCH BIT(31)
  105. #define SD_SWITCH_ALL_GROUPS_MASK GENMASK(23, 0)
  106. struct mmc_cmd {
  107. unsigned int cmd_idx;
  108. unsigned int cmd_arg;
  109. unsigned int resp_type;
  110. unsigned int resp_data[4];
  111. };
  112. struct mmc_ops {
  113. void (*init)(void);
  114. int (*send_cmd)(struct mmc_cmd *cmd);
  115. int (*set_ios)(unsigned int clk, unsigned int width);
  116. int (*prepare)(int lba, uintptr_t buf, size_t size);
  117. int (*read)(int lba, uintptr_t buf, size_t size);
  118. int (*write)(int lba, const uintptr_t buf, size_t size);
  119. };
  120. struct mmc_csd_emmc {
  121. unsigned int not_used: 1;
  122. unsigned int crc: 7;
  123. unsigned int ecc: 2;
  124. unsigned int file_format: 2;
  125. unsigned int tmp_write_protect: 1;
  126. unsigned int perm_write_protect: 1;
  127. unsigned int copy: 1;
  128. unsigned int file_format_grp: 1;
  129. unsigned int reserved_1: 5;
  130. unsigned int write_bl_partial: 1;
  131. unsigned int write_bl_len: 4;
  132. unsigned int r2w_factor: 3;
  133. unsigned int default_ecc: 2;
  134. unsigned int wp_grp_enable: 1;
  135. unsigned int wp_grp_size: 5;
  136. unsigned int erase_grp_mult: 5;
  137. unsigned int erase_grp_size: 5;
  138. unsigned int c_size_mult: 3;
  139. unsigned int vdd_w_curr_max: 3;
  140. unsigned int vdd_w_curr_min: 3;
  141. unsigned int vdd_r_curr_max: 3;
  142. unsigned int vdd_r_curr_min: 3;
  143. unsigned int c_size_low: 2;
  144. unsigned int c_size_high: 10;
  145. unsigned int reserved_2: 2;
  146. unsigned int dsr_imp: 1;
  147. unsigned int read_blk_misalign: 1;
  148. unsigned int write_blk_misalign: 1;
  149. unsigned int read_bl_partial: 1;
  150. unsigned int read_bl_len: 4;
  151. unsigned int ccc: 12;
  152. unsigned int tran_speed: 8;
  153. unsigned int nsac: 8;
  154. unsigned int taac: 8;
  155. unsigned int reserved_3: 2;
  156. unsigned int spec_vers: 4;
  157. unsigned int csd_structure: 2;
  158. };
  159. struct mmc_csd_sd_v2 {
  160. unsigned int not_used: 1;
  161. unsigned int crc: 7;
  162. unsigned int reserved_1: 2;
  163. unsigned int file_format: 2;
  164. unsigned int tmp_write_protect: 1;
  165. unsigned int perm_write_protect: 1;
  166. unsigned int copy: 1;
  167. unsigned int file_format_grp: 1;
  168. unsigned int reserved_2: 5;
  169. unsigned int write_bl_partial: 1;
  170. unsigned int write_bl_len: 4;
  171. unsigned int r2w_factor: 3;
  172. unsigned int reserved_3: 2;
  173. unsigned int wp_grp_enable: 1;
  174. unsigned int wp_grp_size: 7;
  175. unsigned int sector_size: 7;
  176. unsigned int erase_block_en: 1;
  177. unsigned int reserved_4: 1;
  178. unsigned int c_size_low: 16;
  179. unsigned int c_size_high: 6;
  180. unsigned int reserved_5: 6;
  181. unsigned int dsr_imp: 1;
  182. unsigned int read_blk_misalign: 1;
  183. unsigned int write_blk_misalign: 1;
  184. unsigned int read_bl_partial: 1;
  185. unsigned int read_bl_len: 4;
  186. unsigned int ccc: 12;
  187. unsigned int tran_speed: 8;
  188. unsigned int nsac: 8;
  189. unsigned int taac: 8;
  190. unsigned int reserved_6: 6;
  191. unsigned int csd_structure: 2;
  192. };
  193. struct sd_switch_status {
  194. unsigned short max_current;
  195. unsigned short support_g6;
  196. unsigned short support_g5;
  197. unsigned short support_g4;
  198. unsigned short support_g3;
  199. unsigned short support_g2;
  200. unsigned short support_g1;
  201. unsigned char sel_g6_g5;
  202. unsigned char sel_g4_g3;
  203. unsigned char sel_g2_g1;
  204. unsigned char data_struct_ver;
  205. unsigned short busy_g6;
  206. unsigned short busy_g5;
  207. unsigned short busy_g4;
  208. unsigned short busy_g3;
  209. unsigned short busy_g2;
  210. unsigned short busy_g1;
  211. unsigned short reserved[17];
  212. };
  213. enum mmc_device_type {
  214. MMC_IS_EMMC,
  215. MMC_IS_SD,
  216. MMC_IS_SD_HC,
  217. };
  218. struct mmc_device_info {
  219. unsigned long long device_size; /* Size of device in bytes */
  220. unsigned int block_size; /* Block size in bytes */
  221. unsigned int max_bus_freq; /* Max bus freq in Hz */
  222. unsigned int ocr_voltage; /* OCR voltage */
  223. enum mmc_device_type mmc_dev_type; /* Type of MMC */
  224. };
  225. size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size);
  226. size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size);
  227. size_t mmc_erase_blocks(int lba, size_t size);
  228. int mmc_part_switch_current_boot(void);
  229. int mmc_part_switch_user(void);
  230. size_t mmc_boot_part_size(void);
  231. size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size);
  232. int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
  233. unsigned int width, unsigned int flags,
  234. struct mmc_device_info *device_info);
  235. #endif /* MMC_H */