stm32mp157a-avenger96.dts 6.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * Copyright (C) Arrow Electronics 2019 - All Rights Reserved
  4. * Author: Botond Kardos <botond.kardos@arroweurope.com>
  5. *
  6. * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
  7. * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  8. */
  9. /dts-v1/;
  10. #include "stm32mp157.dtsi"
  11. #include "stm32mp15-pinctrl.dtsi"
  12. #include "stm32mp15xxac-pinctrl.dtsi"
  13. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  14. #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  15. / {
  16. model = "Arrow Electronics STM32MP157A Avenger96 board";
  17. compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
  18. aliases {
  19. mmc0 = &sdmmc1;
  20. serial0 = &uart4;
  21. serial1 = &uart7;
  22. };
  23. chosen {
  24. stdout-path = "serial0:115200n8";
  25. };
  26. memory@c0000000 {
  27. device_type = "memory";
  28. reg = <0xc0000000 0x40000000>;
  29. };
  30. };
  31. &i2c4 {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&i2c4_pins_a>;
  34. i2c-scl-rising-time-ns = <185>;
  35. i2c-scl-falling-time-ns = <20>;
  36. status = "okay";
  37. pmic: stpmic@33 {
  38. compatible = "st,stpmic1";
  39. reg = <0x33>;
  40. interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
  41. interrupt-controller;
  42. #interrupt-cells = <2>;
  43. status = "okay";
  44. st,main-control-register = <0x04>;
  45. st,vin-control-register = <0xc0>;
  46. st,usb-control-register = <0x30>;
  47. regulators {
  48. compatible = "st,stpmic1-regulators";
  49. ldo1-supply = <&v3v3>;
  50. ldo2-supply = <&v3v3>;
  51. ldo3-supply = <&vdd_ddr>;
  52. ldo5-supply = <&v3v3>;
  53. ldo6-supply = <&v3v3>;
  54. pwr_sw1-supply = <&bst_out>;
  55. pwr_sw2-supply = <&bst_out>;
  56. vddcore: buck1 {
  57. regulator-name = "vddcore";
  58. regulator-min-microvolt = <1200000>;
  59. regulator-max-microvolt = <1350000>;
  60. regulator-always-on;
  61. regulator-initial-mode = <0>;
  62. regulator-over-current-protection;
  63. };
  64. vdd_ddr: buck2 {
  65. regulator-name = "vdd_ddr";
  66. regulator-min-microvolt = <1350000>;
  67. regulator-max-microvolt = <1350000>;
  68. regulator-always-on;
  69. regulator-initial-mode = <0>;
  70. regulator-over-current-protection;
  71. };
  72. vdd: buck3 {
  73. regulator-name = "vdd";
  74. regulator-min-microvolt = <3300000>;
  75. regulator-max-microvolt = <3300000>;
  76. regulator-always-on;
  77. st,mask-reset;
  78. regulator-initial-mode = <0>;
  79. regulator-over-current-protection;
  80. };
  81. v3v3: buck4 {
  82. regulator-name = "v3v3";
  83. regulator-min-microvolt = <3300000>;
  84. regulator-max-microvolt = <3300000>;
  85. regulator-always-on;
  86. regulator-over-current-protection;
  87. regulator-initial-mode = <0>;
  88. };
  89. vdda: ldo1 {
  90. regulator-name = "vdda";
  91. regulator-min-microvolt = <2900000>;
  92. regulator-max-microvolt = <2900000>;
  93. };
  94. v2v8: ldo2 {
  95. regulator-name = "v2v8";
  96. regulator-min-microvolt = <2800000>;
  97. regulator-max-microvolt = <2800000>;
  98. };
  99. vtt_ddr: ldo3 {
  100. regulator-name = "vtt_ddr";
  101. regulator-always-on;
  102. regulator-over-current-protection;
  103. st,regulator-sink-source;
  104. };
  105. vdd_usb: ldo4 {
  106. regulator-name = "vdd_usb";
  107. regulator-min-microvolt = <3300000>;
  108. regulator-max-microvolt = <3300000>;
  109. };
  110. vdd_sd: ldo5 {
  111. regulator-name = "vdd_sd";
  112. regulator-min-microvolt = <2900000>;
  113. regulator-max-microvolt = <2900000>;
  114. regulator-boot-on;
  115. };
  116. v1v8: ldo6 {
  117. regulator-name = "v1v8";
  118. regulator-min-microvolt = <1800000>;
  119. regulator-max-microvolt = <1800000>;
  120. };
  121. vref_ddr: vref_ddr {
  122. regulator-name = "vref_ddr";
  123. regulator-always-on;
  124. };
  125. bst_out: boost {
  126. regulator-name = "bst_out";
  127. };
  128. vbus_otg: pwr_sw1 {
  129. regulator-name = "vbus_otg";
  130. };
  131. vbus_sw: pwr_sw2 {
  132. regulator-name = "vbus_sw";
  133. regulator-active-discharge = <1>;
  134. };
  135. };
  136. };
  137. };
  138. &iwdg2 {
  139. timeout-sec = <32>;
  140. status = "okay";
  141. };
  142. &pwr_regulators {
  143. vdd-supply = <&vdd>;
  144. vdd_3v3_usbfs-supply = <&vdd_usb>;
  145. };
  146. &rcc {
  147. st,clksrc = <
  148. CLK_MPU_PLL1P
  149. CLK_AXI_PLL2P
  150. CLK_MCU_PLL3P
  151. CLK_RTC_LSE
  152. CLK_MCO1_DISABLED
  153. CLK_MCO2_DISABLED
  154. CLK_CKPER_HSE
  155. CLK_FMC_ACLK
  156. CLK_QSPI_ACLK
  157. CLK_ETH_DISABLED
  158. CLK_SDMMC12_PLL4P
  159. CLK_DSI_DSIPLL
  160. CLK_STGEN_HSE
  161. CLK_USBPHY_HSE
  162. CLK_SPI2S1_PLL3Q
  163. CLK_SPI2S23_PLL3Q
  164. CLK_SPI45_HSI
  165. CLK_SPI6_HSI
  166. CLK_I2C46_HSI
  167. CLK_SDMMC3_PLL4P
  168. CLK_USBO_USBPHY
  169. CLK_ADC_CKPER
  170. CLK_CEC_LSE
  171. CLK_I2C12_HSI
  172. CLK_I2C35_HSI
  173. CLK_UART1_HSI
  174. CLK_UART24_HSI
  175. CLK_UART35_HSI
  176. CLK_UART6_HSI
  177. CLK_UART78_HSI
  178. CLK_SPDIF_PLL4P
  179. CLK_FDCAN_PLL4R
  180. CLK_SAI1_PLL3Q
  181. CLK_SAI2_PLL3Q
  182. CLK_SAI3_PLL3Q
  183. CLK_SAI4_PLL3Q
  184. CLK_RNG1_CSI
  185. CLK_RNG2_LSI
  186. CLK_LPTIM1_PCLK1
  187. CLK_LPTIM23_PCLK3
  188. CLK_LPTIM45_LSE
  189. >;
  190. st,clkdiv = <
  191. DIV(DIV_MPU, 1)
  192. DIV(DIV_AXI, 0)
  193. DIV(DIV_MCU, 0)
  194. DIV(DIV_APB1, 1)
  195. DIV(DIV_APB2, 1)
  196. DIV(DIV_APB3, 1)
  197. DIV(DIV_APB4, 1)
  198. DIV(DIV_APB5, 2)
  199. DIV(DIV_RTC, 23)
  200. DIV(DIV_MCO1, 0)
  201. DIV(DIV_MCO2, 0)
  202. >;
  203. st,pll_vco {
  204. pll2_vco_1066Mhz: pll2-vco-1066Mhz {
  205. src = <CLK_PLL12_HSE>;
  206. divmn = <2 65>;
  207. frac = <0x1400>;
  208. };
  209. pll3_vco_417Mhz: pll3-vco-417Mhz {
  210. src = <CLK_PLL3_HSE>;
  211. divmn = <1 33>;
  212. frac = <0x1a04>;
  213. };
  214. pll4_vco_480Mhz: pll4-vco-480Mhz {
  215. src = <CLK_PLL4_HSE>;
  216. divmn = <1 39>;
  217. };
  218. };
  219. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  220. pll2: st,pll@1 {
  221. compatible = "st,stm32mp1-pll";
  222. reg = <1>;
  223. st,pll = <&pll2_cfg1>;
  224. pll2_cfg1: pll2_cfg1 {
  225. st,pll_vco = <&pll2_vco_1066Mhz>;
  226. st,pll_div_pqr = <1 0 0>;
  227. };
  228. };
  229. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  230. pll3: st,pll@2 {
  231. compatible = "st,stm32mp1-pll";
  232. reg = <2>;
  233. st,pll = <&pll3_cfg1>;
  234. pll3_cfg1: pll3_cfg1 {
  235. st,pll_vco = <&pll3_vco_417Mhz>;
  236. st,pll_div_pqr = <1 16 36>;
  237. };
  238. };
  239. /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
  240. pll4: st,pll@3 {
  241. compatible = "st,stm32mp1-pll";
  242. reg = <3>;
  243. st,pll = <&pll4_cfg1>;
  244. pll4_cfg1: pll4_cfg1 {
  245. st,pll_vco = <&pll4_vco_480Mhz>;
  246. st,pll_div_pqr = <3 11 4>;
  247. };
  248. };
  249. };
  250. &rng1 {
  251. status = "okay";
  252. };
  253. &rtc {
  254. status = "okay";
  255. };
  256. &sdmmc1 {
  257. pinctrl-names = "default";
  258. pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
  259. st,sig-dir;
  260. st,neg-edge;
  261. st,use-ckin;
  262. bus-width = <4>;
  263. vmmc-supply = <&vdd_sd>;
  264. status = "okay";
  265. };
  266. &uart4 {
  267. /* On Low speed expansion header */
  268. label = "LS-UART1";
  269. pinctrl-names = "default";
  270. pinctrl-0 = <&uart4_pins_b>;
  271. status = "okay";
  272. };
  273. &uart7 {
  274. /* On Low speed expansion header */
  275. label = "LS-UART0";
  276. pinctrl-names = "default";
  277. pinctrl-0 = <&uart7_pins_a>;
  278. status = "okay";
  279. };