plat_macros.S 3.1 KB

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  1. /*
  2. * Copyright (c) 2014-2024, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #ifndef ROCKCHIP_PLAT_MACROS_S
  7. #define ROCKCHIP_PLAT_MACROS_S
  8. #include <drivers/arm/cci.h>
  9. #include <drivers/arm/gic_common.h>
  10. #include <drivers/arm/gicv2.h>
  11. #include <drivers/arm/gicv3.h>
  12. #include <platform_def.h>
  13. .section .rodata.gic_reg_name, "aS"
  14. /* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
  15. gicc_regs:
  16. .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
  17. /* Applicable only to GICv3 with SRE enabled */
  18. icc_regs:
  19. .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
  20. /* Registers common to both GICv2 and GICv3 */
  21. gicd_pend_reg:
  22. .ascii "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
  23. " Offset:\t\t\tvalue\n\0"
  24. newline:
  25. .asciz "\n"
  26. spacer:
  27. .asciz ":\t\t0x"
  28. .section .rodata.cci_reg_name, "aS"
  29. cci_iface_regs:
  30. .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
  31. /* ---------------------------------------------
  32. * The below utility macro prints out relevant GIC
  33. * and CCI registers whenever an unhandled
  34. * exception is taken in BL31.
  35. * Expects: GICD base in x26, GICC base in x27
  36. * Clobbers: x0 - x10, sp
  37. * ---------------------------------------------
  38. */
  39. .macro plat_crash_print_regs
  40. mov_imm x26, PLAT_RK_GICD_BASE
  41. mov_imm x27, PLAT_RK_GICC_BASE
  42. /* Check for GICv3 system register access */
  43. mrs x7, id_aa64pfr0_el1
  44. ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
  45. cmp x7, #1
  46. b.ne print_gicv2
  47. /* Check for SRE enable */
  48. mrs x8, ICC_SRE_EL3
  49. tst x8, #ICC_SRE_SRE_BIT
  50. b.eq print_gicv2
  51. /* Load the icc reg list to x6 */
  52. adr x6, icc_regs
  53. /* Load the icc regs to gp regs used by str_in_crash_buf_print */
  54. mrs x8, ICC_HPPIR0_EL1
  55. mrs x9, ICC_HPPIR1_EL1
  56. mrs x10, ICC_CTLR_EL3
  57. /* Store to the crash buf and print to console */
  58. bl str_in_crash_buf_print
  59. b print_gic_common
  60. print_gicv2:
  61. /* Load the gicc reg list to x6 */
  62. adr x6, gicc_regs
  63. /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
  64. ldr w8, [x27, #GICC_HPPIR]
  65. ldr w9, [x27, #GICC_AHPPIR]
  66. ldr w10, [x27, #GICC_CTLR]
  67. /* Store to the crash buf and print to console */
  68. bl str_in_crash_buf_print
  69. print_gic_common:
  70. /* Print the GICD_ISPENDR regs */
  71. add x7, x26, #GICD_ISPENDR
  72. adr x4, gicd_pend_reg
  73. bl asm_print_str
  74. gicd_ispendr_loop:
  75. sub x4, x7, x26
  76. cmp x4, #0x280
  77. b.eq exit_print_gic_regs
  78. bl asm_print_hex
  79. adr x4, spacer
  80. bl asm_print_str
  81. ldr x4, [x7], #8
  82. bl asm_print_hex
  83. adr x4, newline
  84. bl asm_print_str
  85. b gicd_ispendr_loop
  86. exit_print_gic_regs:
  87. #if PLATFORM_CLUSTER_COUNT > 1
  88. adr x6, cci_iface_regs
  89. /* Store in x7 the base address of the first interface */
  90. mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \
  91. PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX))
  92. ldr w8, [x7, #SNOOP_CTRL_REG]
  93. /* Store in x7 the base address of the second interface */
  94. mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \
  95. PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX))
  96. ldr w9, [x7, #SNOOP_CTRL_REG]
  97. /* Store to the crash buf and print to console */
  98. bl str_in_crash_buf_print
  99. #endif
  100. .endm
  101. #endif /* ROCKCHIP_PLAT_MACROS_S */