stm32mp157c-ed1.dts 6.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
  4. * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
  5. */
  6. /dts-v1/;
  7. #include "stm32mp157.dtsi"
  8. #include "stm32mp15xc.dtsi"
  9. #include "stm32mp15-pinctrl.dtsi"
  10. #include "stm32mp15xxaa-pinctrl.dtsi"
  11. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  12. #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  13. / {
  14. model = "STMicroelectronics STM32MP157C eval daughter";
  15. compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. memory@c0000000 {
  20. device_type = "memory";
  21. reg = <0xC0000000 0x40000000>;
  22. };
  23. aliases {
  24. serial0 = &uart4;
  25. };
  26. };
  27. &bsec {
  28. board_id: board_id@ec {
  29. reg = <0xec 0x4>;
  30. st,non-secure-otp;
  31. };
  32. };
  33. &clk_hse {
  34. st,digbypass;
  35. };
  36. &cpu0 {
  37. cpu-supply = <&vddcore>;
  38. };
  39. &cpu1 {
  40. cpu-supply = <&vddcore>;
  41. };
  42. &cryp1 {
  43. status = "okay";
  44. };
  45. &hash1 {
  46. status = "okay";
  47. };
  48. &i2c4 {
  49. pinctrl-names = "default";
  50. pinctrl-0 = <&i2c4_pins_a>;
  51. i2c-scl-rising-time-ns = <185>;
  52. i2c-scl-falling-time-ns = <20>;
  53. clock-frequency = <400000>;
  54. status = "okay";
  55. pmic: stpmic@33 {
  56. compatible = "st,stpmic1";
  57. reg = <0x33>;
  58. interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
  59. interrupt-controller;
  60. #interrupt-cells = <2>;
  61. status = "okay";
  62. regulators {
  63. compatible = "st,stpmic1-regulators";
  64. ldo1-supply = <&v3v3>;
  65. ldo2-supply = <&v3v3>;
  66. ldo3-supply = <&vdd_ddr>;
  67. ldo5-supply = <&v3v3>;
  68. ldo6-supply = <&v3v3>;
  69. pwr_sw1-supply = <&bst_out>;
  70. pwr_sw2-supply = <&bst_out>;
  71. vddcore: buck1 {
  72. regulator-name = "vddcore";
  73. regulator-min-microvolt = <1200000>;
  74. regulator-max-microvolt = <1350000>;
  75. regulator-always-on;
  76. regulator-initial-mode = <0>;
  77. regulator-over-current-protection;
  78. };
  79. vdd_ddr: buck2 {
  80. regulator-name = "vdd_ddr";
  81. regulator-min-microvolt = <1350000>;
  82. regulator-max-microvolt = <1350000>;
  83. regulator-always-on;
  84. regulator-initial-mode = <0>;
  85. regulator-over-current-protection;
  86. };
  87. vdd: buck3 {
  88. regulator-name = "vdd";
  89. regulator-min-microvolt = <3300000>;
  90. regulator-max-microvolt = <3300000>;
  91. regulator-always-on;
  92. st,mask-reset;
  93. regulator-initial-mode = <0>;
  94. regulator-over-current-protection;
  95. };
  96. v3v3: buck4 {
  97. regulator-name = "v3v3";
  98. regulator-min-microvolt = <3300000>;
  99. regulator-max-microvolt = <3300000>;
  100. regulator-always-on;
  101. regulator-over-current-protection;
  102. regulator-initial-mode = <0>;
  103. };
  104. vdda: ldo1 {
  105. regulator-name = "vdda";
  106. regulator-min-microvolt = <2900000>;
  107. regulator-max-microvolt = <2900000>;
  108. };
  109. v2v8: ldo2 {
  110. regulator-name = "v2v8";
  111. regulator-min-microvolt = <2800000>;
  112. regulator-max-microvolt = <2800000>;
  113. };
  114. vtt_ddr: ldo3 {
  115. regulator-name = "vtt_ddr";
  116. regulator-always-on;
  117. regulator-over-current-protection;
  118. st,regulator-sink-source;
  119. };
  120. vdd_usb: ldo4 {
  121. regulator-name = "vdd_usb";
  122. regulator-min-microvolt = <3300000>;
  123. regulator-max-microvolt = <3300000>;
  124. };
  125. vdd_sd: ldo5 {
  126. regulator-name = "vdd_sd";
  127. regulator-min-microvolt = <2900000>;
  128. regulator-max-microvolt = <2900000>;
  129. regulator-boot-on;
  130. };
  131. v1v8: ldo6 {
  132. regulator-name = "v1v8";
  133. regulator-min-microvolt = <1800000>;
  134. regulator-max-microvolt = <1800000>;
  135. };
  136. vref_ddr: vref_ddr {
  137. regulator-name = "vref_ddr";
  138. regulator-always-on;
  139. };
  140. bst_out: boost {
  141. regulator-name = "bst_out";
  142. };
  143. vbus_otg: pwr_sw1 {
  144. regulator-name = "vbus_otg";
  145. };
  146. vbus_sw: pwr_sw2 {
  147. regulator-name = "vbus_sw";
  148. regulator-active-discharge = <1>;
  149. };
  150. };
  151. };
  152. };
  153. &iwdg2 {
  154. timeout-sec = <32>;
  155. status = "okay";
  156. };
  157. &pwr_regulators {
  158. vdd-supply = <&vdd>;
  159. vdd_3v3_usbfs-supply = <&vdd_usb>;
  160. };
  161. &rcc {
  162. st,clksrc = <
  163. CLK_MPU_PLL1P
  164. CLK_AXI_PLL2P
  165. CLK_MCU_PLL3P
  166. CLK_PLL12_HSE
  167. CLK_PLL3_HSE
  168. CLK_PLL4_HSE
  169. CLK_RTC_LSE
  170. CLK_MCO1_DISABLED
  171. CLK_MCO2_DISABLED
  172. >;
  173. st,clkdiv = <
  174. 1 /*MPU*/
  175. 0 /*AXI*/
  176. 0 /*MCU*/
  177. 1 /*APB1*/
  178. 1 /*APB2*/
  179. 1 /*APB3*/
  180. 1 /*APB4*/
  181. 2 /*APB5*/
  182. 23 /*RTC*/
  183. 0 /*MCO1*/
  184. 0 /*MCO2*/
  185. >;
  186. st,pkcs = <
  187. CLK_CKPER_HSE
  188. CLK_FMC_ACLK
  189. CLK_QSPI_ACLK
  190. CLK_ETH_PLL4P
  191. CLK_SDMMC12_PLL4P
  192. CLK_DSI_DSIPLL
  193. CLK_STGEN_HSE
  194. CLK_USBPHY_HSE
  195. CLK_SPI2S1_PLL3Q
  196. CLK_SPI2S23_PLL3Q
  197. CLK_SPI45_HSI
  198. CLK_SPI6_HSI
  199. CLK_I2C46_HSI
  200. CLK_SDMMC3_PLL4P
  201. CLK_USBO_USBPHY
  202. CLK_ADC_CKPER
  203. CLK_CEC_LSE
  204. CLK_I2C12_HSI
  205. CLK_I2C35_HSI
  206. CLK_UART1_HSI
  207. CLK_UART24_HSI
  208. CLK_UART35_HSI
  209. CLK_UART6_HSI
  210. CLK_UART78_HSI
  211. CLK_SPDIF_PLL4P
  212. CLK_FDCAN_PLL4R
  213. CLK_SAI1_PLL3Q
  214. CLK_SAI2_PLL3Q
  215. CLK_SAI3_PLL3Q
  216. CLK_SAI4_PLL3Q
  217. CLK_RNG1_LSI
  218. CLK_RNG2_LSI
  219. CLK_LPTIM1_PCLK1
  220. CLK_LPTIM23_PCLK3
  221. CLK_LPTIM45_LSE
  222. >;
  223. /* VCO = 1300.0 MHz => P = 650 (CPU) */
  224. pll1: st,pll@0 {
  225. compatible = "st,stm32mp1-pll";
  226. reg = <0>;
  227. cfg = <2 80 0 0 0 PQR(1,0,0)>;
  228. frac = <0x800>;
  229. };
  230. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  231. pll2: st,pll@1 {
  232. compatible = "st,stm32mp1-pll";
  233. reg = <1>;
  234. cfg = <2 65 1 0 0 PQR(1,1,1)>;
  235. frac = <0x1400>;
  236. };
  237. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  238. pll3: st,pll@2 {
  239. compatible = "st,stm32mp1-pll";
  240. reg = <2>;
  241. cfg = <1 33 1 16 36 PQR(1,1,1)>;
  242. frac = <0x1a04>;
  243. };
  244. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  245. pll4: st,pll@3 {
  246. compatible = "st,stm32mp1-pll";
  247. reg = <3>;
  248. cfg = <3 98 5 7 7 PQR(1,1,1)>;
  249. };
  250. };
  251. &rng1 {
  252. status = "okay";
  253. };
  254. &rtc {
  255. status = "okay";
  256. };
  257. &sdmmc1 {
  258. pinctrl-names = "default";
  259. pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
  260. disable-wp;
  261. st,sig-dir;
  262. st,neg-edge;
  263. st,use-ckin;
  264. bus-width = <4>;
  265. vmmc-supply = <&vdd_sd>;
  266. sd-uhs-sdr12;
  267. sd-uhs-sdr25;
  268. sd-uhs-sdr50;
  269. sd-uhs-ddr50;
  270. status = "okay";
  271. };
  272. &sdmmc2 {
  273. pinctrl-names = "default";
  274. pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
  275. non-removable;
  276. no-sd;
  277. no-sdio;
  278. st,neg-edge;
  279. bus-width = <8>;
  280. vmmc-supply = <&v3v3>;
  281. vqmmc-supply = <&vdd>;
  282. mmc-ddr-3_3v;
  283. status = "okay";
  284. };
  285. &uart4 {
  286. pinctrl-names = "default";
  287. pinctrl-0 = <&uart4_pins_a>;
  288. status = "okay";
  289. };