stm32mp251.dtsi 6.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
  2. /*
  3. * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
  4. * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  5. */
  6. #include <dt-bindings/clock/stm32mp25-clks.h>
  7. #include <dt-bindings/interrupt-controller/arm-gic.h>
  8. #include <dt-bindings/reset/stm32mp25-resets.h>
  9. / {
  10. #address-cells = <2>;
  11. #size-cells = <2>;
  12. cpus {
  13. #address-cells = <1>;
  14. #size-cells = <0>;
  15. cpu0: cpu@0 {
  16. compatible = "arm,cortex-a35";
  17. device_type = "cpu";
  18. reg = <0>;
  19. enable-method = "psci";
  20. };
  21. };
  22. clocks {
  23. clk_hse: clk-hse {
  24. #clock-cells = <0>;
  25. compatible = "fixed-clock";
  26. clock-frequency = <48000000>;
  27. };
  28. clk_hsi: clk-hsi {
  29. #clock-cells = <0>;
  30. compatible = "fixed-clock";
  31. clock-frequency = <64000000>;
  32. };
  33. clk_lse: clk-lse {
  34. #clock-cells = <0>;
  35. compatible = "fixed-clock";
  36. clock-frequency = <32768>;
  37. };
  38. clk_lsi: clk-lsi {
  39. #clock-cells = <0>;
  40. compatible = "fixed-clock";
  41. clock-frequency = <32000>;
  42. };
  43. clk_msi: clk-msi {
  44. #clock-cells = <0>;
  45. compatible = "fixed-clock";
  46. clock-frequency = <16000000>;
  47. };
  48. };
  49. intc: interrupt-controller@4ac00000 {
  50. compatible = "arm,cortex-a7-gic";
  51. #interrupt-cells = <3>;
  52. #address-cells = <1>;
  53. interrupt-controller;
  54. reg = <0x0 0x4ac10000 0x0 0x1000>,
  55. <0x0 0x4ac20000 0x0 0x2000>,
  56. <0x0 0x4ac40000 0x0 0x2000>,
  57. <0x0 0x4ac60000 0x0 0x2000>;
  58. };
  59. timer: timer {
  60. compatible = "arm,armv8-timer";
  61. interrupt-parent = <&intc>;
  62. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  63. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  64. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  65. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  66. always-on;
  67. };
  68. soc@0 {
  69. compatible = "simple-bus";
  70. #address-cells = <1>;
  71. #size-cells = <1>;
  72. interrupt-parent = <&intc>;
  73. ranges = <0x0 0x0 0x0 0x80000000>;
  74. rifsc: rifsc@42080000 {
  75. compatible = "st,stm32mp25-rifsc";
  76. reg = <0x42080000 0x1000>;
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. usart2: serial@400e0000 {
  80. compatible = "st,stm32h7-uart";
  81. reg = <0x400e0000 0x400>;
  82. clocks = <&rcc CK_KER_USART2>;
  83. resets = <&rcc USART2_R>;
  84. status = "disabled";
  85. };
  86. };
  87. rcc: rcc@44200000 {
  88. compatible = "st,stm32mp25-rcc";
  89. reg = <0x44200000 0x10000>;
  90. #clock-cells = <1>;
  91. #reset-cells = <1>;
  92. };
  93. pwr: pwr@44210000 {
  94. compatible = "st,stm32mp25-pwr";
  95. reg = <0x44210000 0x400>;
  96. vddio1: vddio1 {
  97. regulator-name = "vddio1";
  98. };
  99. vddio2: vddio2 {
  100. regulator-name = "vddio2";
  101. };
  102. vddio3: vddio3 {
  103. regulator-name = "vddio3";
  104. };
  105. vddio4: vddio4 {
  106. regulator-name = "vddio4";
  107. };
  108. vddio: vddio {
  109. regulator-name = "vddio";
  110. };
  111. };
  112. syscfg: syscon@44230000 {
  113. compatible = "st,stm32mp25-syscfg", "syscon";
  114. reg = <0x44230000 0x10000>;
  115. };
  116. pinctrl: pinctrl@44240000 {
  117. #address-cells = <1>;
  118. #size-cells = <1>;
  119. compatible = "st,stm32mp257-pinctrl";
  120. ranges = <0 0x44240000 0xa0400>;
  121. pins-are-numbered;
  122. gpioa: gpio@44240000 {
  123. gpio-controller;
  124. #gpio-cells = <2>;
  125. interrupt-controller;
  126. #interrupt-cells = <2>;
  127. reg = <0x0 0x400>;
  128. clocks = <&rcc CK_BUS_GPIOA>;
  129. st,bank-name = "GPIOA";
  130. status = "disabled";
  131. };
  132. gpiob: gpio@44250000 {
  133. gpio-controller;
  134. #gpio-cells = <2>;
  135. interrupt-controller;
  136. #interrupt-cells = <2>;
  137. reg = <0x10000 0x400>;
  138. clocks = <&rcc CK_BUS_GPIOB>;
  139. st,bank-name = "GPIOB";
  140. status = "disabled";
  141. };
  142. gpioc: gpio@44260000 {
  143. gpio-controller;
  144. #gpio-cells = <2>;
  145. interrupt-controller;
  146. #interrupt-cells = <2>;
  147. reg = <0x20000 0x400>;
  148. clocks = <&rcc CK_BUS_GPIOC>;
  149. st,bank-name = "GPIOC";
  150. status = "disabled";
  151. };
  152. gpiod: gpio@44270000 {
  153. gpio-controller;
  154. #gpio-cells = <2>;
  155. interrupt-controller;
  156. #interrupt-cells = <2>;
  157. reg = <0x30000 0x400>;
  158. clocks = <&rcc CK_BUS_GPIOD>;
  159. st,bank-name = "GPIOD";
  160. status = "disabled";
  161. };
  162. gpioe: gpio@44280000 {
  163. gpio-controller;
  164. #gpio-cells = <2>;
  165. interrupt-controller;
  166. #interrupt-cells = <2>;
  167. reg = <0x40000 0x400>;
  168. clocks = <&rcc CK_BUS_GPIOE>;
  169. st,bank-name = "GPIOE";
  170. status = "disabled";
  171. };
  172. gpiof: gpio@44290000 {
  173. gpio-controller;
  174. #gpio-cells = <2>;
  175. interrupt-controller;
  176. #interrupt-cells = <2>;
  177. reg = <0x50000 0x400>;
  178. clocks = <&rcc CK_BUS_GPIOF>;
  179. st,bank-name = "GPIOF";
  180. status = "disabled";
  181. };
  182. gpiog: gpio@442a0000 {
  183. gpio-controller;
  184. #gpio-cells = <2>;
  185. interrupt-controller;
  186. #interrupt-cells = <2>;
  187. reg = <0x60000 0x400>;
  188. clocks = <&rcc CK_BUS_GPIOG>;
  189. st,bank-name = "GPIOG";
  190. status = "disabled";
  191. };
  192. gpioh: gpio@442b0000 {
  193. gpio-controller;
  194. #gpio-cells = <2>;
  195. interrupt-controller;
  196. #interrupt-cells = <2>;
  197. reg = <0x70000 0x400>;
  198. clocks = <&rcc CK_BUS_GPIOH>;
  199. st,bank-name = "GPIOH";
  200. status = "disabled";
  201. };
  202. gpioi: gpio@442c0000 {
  203. gpio-controller;
  204. #gpio-cells = <2>;
  205. interrupt-controller;
  206. #interrupt-cells = <2>;
  207. reg = <0x80000 0x400>;
  208. clocks = <&rcc CK_BUS_GPIOI>;
  209. st,bank-name = "GPIOI";
  210. status = "disabled";
  211. };
  212. gpioj: gpio@442d0000 {
  213. gpio-controller;
  214. #gpio-cells = <2>;
  215. interrupt-controller;
  216. #interrupt-cells = <2>;
  217. reg = <0x90000 0x400>;
  218. clocks = <&rcc CK_BUS_GPIOJ>;
  219. st,bank-name = "GPIOJ";
  220. status = "disabled";
  221. };
  222. gpiok: gpio@442e0000 {
  223. gpio-controller;
  224. #gpio-cells = <2>;
  225. interrupt-controller;
  226. #interrupt-cells = <2>;
  227. reg = <0xa0000 0x400>;
  228. clocks = <&rcc CK_BUS_GPIOK>;
  229. st,bank-name = "GPIOK";
  230. status = "disabled";
  231. };
  232. };
  233. pinctrl_z: pinctrl@46200000 {
  234. #address-cells = <1>;
  235. #size-cells = <1>;
  236. compatible = "st,stm32mp257-z-pinctrl";
  237. ranges = <0 0x46200000 0x400>;
  238. pins-are-numbered;
  239. gpioz: gpio@46200000 {
  240. gpio-controller;
  241. #gpio-cells = <2>;
  242. interrupt-controller;
  243. #interrupt-cells = <2>;
  244. reg = <0 0x400>;
  245. clocks = <&rcc CK_BUS_GPIOZ>;
  246. st,bank-name = "GPIOZ";
  247. st,bank-ioport = <11>;
  248. status = "disabled";
  249. };
  250. };
  251. };
  252. };