tsp_common.c 5.2 KB

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  1. /*
  2. * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <assert.h>
  7. #include <inttypes.h>
  8. #include <stdint.h>
  9. #include <arch_features.h>
  10. #include <arch_helpers.h>
  11. #include <bl32/tsp/tsp.h>
  12. #include <common/bl_common.h>
  13. #include <common/debug.h>
  14. #include <lib/spinlock.h>
  15. #include <plat/common/platform.h>
  16. #include <platform_tsp.h>
  17. #include "tsp_private.h"
  18. #include <platform_def.h>
  19. /*******************************************************************************
  20. * Per cpu data structure to populate parameters for an SMC in C code and use
  21. * a pointer to this structure in assembler code to populate x0-x7.
  22. ******************************************************************************/
  23. static smc_args_t tsp_smc_args[PLATFORM_CORE_COUNT];
  24. /*******************************************************************************
  25. * Per cpu data structure to keep track of TSP activity
  26. ******************************************************************************/
  27. work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
  28. smc_args_t *set_smc_args(uint64_t arg0,
  29. uint64_t arg1,
  30. uint64_t arg2,
  31. uint64_t arg3,
  32. uint64_t arg4,
  33. uint64_t arg5,
  34. uint64_t arg6,
  35. uint64_t arg7)
  36. {
  37. uint32_t linear_id;
  38. smc_args_t *pcpu_smc_args;
  39. /*
  40. * Return to Secure Monitor by raising an SMC. The results of the
  41. * service are passed as an arguments to the SMC.
  42. */
  43. linear_id = plat_my_core_pos();
  44. pcpu_smc_args = &tsp_smc_args[linear_id];
  45. write_sp_arg(pcpu_smc_args, SMC_ARG0, arg0);
  46. write_sp_arg(pcpu_smc_args, SMC_ARG1, arg1);
  47. write_sp_arg(pcpu_smc_args, SMC_ARG2, arg2);
  48. write_sp_arg(pcpu_smc_args, SMC_ARG3, arg3);
  49. write_sp_arg(pcpu_smc_args, SMC_ARG4, arg4);
  50. write_sp_arg(pcpu_smc_args, SMC_ARG5, arg5);
  51. write_sp_arg(pcpu_smc_args, SMC_ARG6, arg6);
  52. write_sp_arg(pcpu_smc_args, SMC_ARG7, arg7);
  53. return pcpu_smc_args;
  54. }
  55. /*******************************************************************************
  56. * Setup function for TSP.
  57. ******************************************************************************/
  58. void tsp_setup(void)
  59. {
  60. /* Enable early console if EARLY_CONSOLE flag is enabled */
  61. plat_setup_early_console();
  62. /* Perform early platform-specific setup. */
  63. tsp_early_platform_setup();
  64. /* Perform late platform-specific setup. */
  65. tsp_plat_arch_setup();
  66. #if ENABLE_PAUTH
  67. /*
  68. * Assert that the ARMv8.3-PAuth registers are present or an access
  69. * fault will be triggered when they are being saved or restored.
  70. */
  71. assert(is_armv8_3_pauth_present());
  72. #endif /* ENABLE_PAUTH */
  73. }
  74. /*******************************************************************************
  75. * This function performs any remaining bookkeeping in the test secure payload
  76. * before the system is switched off (in response to a psci SYSTEM_OFF request).
  77. ******************************************************************************/
  78. smc_args_t *tsp_system_off_main(uint64_t arg0,
  79. uint64_t arg1,
  80. uint64_t arg2,
  81. uint64_t arg3,
  82. uint64_t arg4,
  83. uint64_t arg5,
  84. uint64_t arg6,
  85. uint64_t arg7)
  86. {
  87. uint32_t linear_id = plat_my_core_pos();
  88. /* Update this cpu's statistics. */
  89. tsp_stats[linear_id].smc_count++;
  90. tsp_stats[linear_id].eret_count++;
  91. INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr());
  92. INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
  93. tsp_stats[linear_id].smc_count,
  94. tsp_stats[linear_id].eret_count);
  95. /* Indicate to the SPD that we have completed this request. */
  96. return set_smc_args(TSP_SYSTEM_OFF_DONE, 0, 0, 0, 0, 0, 0, 0);
  97. }
  98. /*******************************************************************************
  99. * This function performs any remaining bookkeeping in the test secure payload
  100. * before the system is reset (in response to a psci SYSTEM_RESET request).
  101. ******************************************************************************/
  102. smc_args_t *tsp_system_reset_main(uint64_t arg0,
  103. uint64_t arg1,
  104. uint64_t arg2,
  105. uint64_t arg3,
  106. uint64_t arg4,
  107. uint64_t arg5,
  108. uint64_t arg6,
  109. uint64_t arg7)
  110. {
  111. uint32_t linear_id = plat_my_core_pos();
  112. /* Update this cpu's statistics. */
  113. tsp_stats[linear_id].smc_count++;
  114. tsp_stats[linear_id].eret_count++;
  115. INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr());
  116. INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
  117. tsp_stats[linear_id].smc_count,
  118. tsp_stats[linear_id].eret_count);
  119. /* Indicate to the SPD that we have completed this request. */
  120. return set_smc_args(TSP_SYSTEM_RESET_DONE, 0, 0, 0, 0, 0, 0, 0);
  121. }
  122. /*******************************************************************************
  123. * TSP smc abort handler. This function is called when aborting a preempted
  124. * yielding SMC request. It should cleanup all resources owned by the SMC
  125. * handler such as locks or dynamically allocated memory so following SMC
  126. * request are executed in a clean environment.
  127. ******************************************************************************/
  128. smc_args_t *tsp_abort_smc_handler(uint64_t func,
  129. uint64_t arg1,
  130. uint64_t arg2,
  131. uint64_t arg3,
  132. uint64_t arg4,
  133. uint64_t arg5,
  134. uint64_t arg6,
  135. uint64_t arg7)
  136. {
  137. return set_smc_args(TSP_ABORT_DONE, 0, 0, 0, 0, 0, 0, 0);
  138. }