rpi3_sdhost.h 3.5 KB

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  1. /*
  2. * Copyright (c) 2019, Linaro Limited
  3. * Copyright (c) 2019, Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
  4. *
  5. * SPDX-License-Identifier: BSD-3-Clause
  6. */
  7. #ifndef RPI3_SDHOST_H
  8. #define RPI3_SDHOST_H
  9. #include <drivers/mmc.h>
  10. #include <stdint.h>
  11. #include <platform_def.h>
  12. struct rpi3_sdhost_params {
  13. uintptr_t reg_base;
  14. uint32_t clk_rate;
  15. uint32_t clk_rate_initial;
  16. uint32_t bus_width;
  17. uint32_t flags;
  18. uint32_t current_cmd;
  19. uint8_t cmdbusy;
  20. uint8_t mmc_app_cmd;
  21. uint32_t ns_per_fifo_word;
  22. uint32_t sdcard_rca;
  23. uint32_t gpio48_pinselect[6];
  24. };
  25. void rpi3_sdhost_init(struct rpi3_sdhost_params *params,
  26. struct mmc_device_info *mmc_dev_info);
  27. void rpi3_sdhost_stop(void);
  28. /* Registers */
  29. #define HC_COMMAND 0x00 /* Command and flags */
  30. #define HC_ARGUMENT 0x04
  31. #define HC_TIMEOUTCOUNTER 0x08
  32. #define HC_CLOCKDIVISOR 0x0c
  33. #define HC_RESPONSE_0 0x10
  34. #define HC_RESPONSE_1 0x14
  35. #define HC_RESPONSE_2 0x18
  36. #define HC_RESPONSE_3 0x1c
  37. #define HC_HOSTSTATUS 0x20
  38. #define HC_POWER 0x30
  39. #define HC_DEBUG 0x34
  40. #define HC_HOSTCONFIG 0x38
  41. #define HC_BLOCKSIZE 0x3c
  42. #define HC_DATAPORT 0x40
  43. #define HC_BLOCKCOUNT 0x50
  44. /* Flags for HC_COMMAND register */
  45. #define HC_CMD_ENABLE 0x8000
  46. #define HC_CMD_FAILED 0x4000
  47. #define HC_CMD_BUSY 0x0800
  48. #define HC_CMD_RESPONSE_NONE 0x0400
  49. #define HC_CMD_RESPONSE_LONG 0x0200
  50. #define HC_CMD_WRITE 0x0080
  51. #define HC_CMD_READ 0x0040
  52. #define HC_CMD_COMMAND_MASK 0x003f
  53. #define RPI3_SDHOST_MAX_CLOCK 250000000 // technically, we should obtain this number from the mailbox
  54. #define HC_CLOCKDIVISOR_MAXVAL 0x07ff
  55. #define HC_CLOCKDIVISOR_PREFERVAL 0x027b
  56. #define HC_CLOCKDIVISOR_SLOWVAL 0x0148
  57. #define HC_CLOCKDIVISOR_STOPVAL 0x01fb
  58. /* Flags for HC_HOSTSTATUS register */
  59. #define HC_HSTST_HAVEDATA 0x0001
  60. #define HC_HSTST_ERROR_FIFO 0x0008
  61. #define HC_HSTST_ERROR_CRC7 0x0010
  62. #define HC_HSTST_ERROR_CRC16 0x0020
  63. #define HC_HSTST_TIMEOUT_CMD 0x0040
  64. #define HC_HSTST_TIMEOUT_DATA 0x0080
  65. #define HC_HSTST_INT_BLOCK 0x0200
  66. #define HC_HSTST_INT_BUSY 0x0400
  67. #define HC_HSTST_RESET 0xffff
  68. #define HC_HSTST_MASK_ERROR_DATA (HC_HSTST_ERROR_FIFO | \
  69. HC_HSTST_ERROR_CRC7 | \
  70. HC_HSTST_ERROR_CRC16 | \
  71. HC_HSTST_TIMEOUT_DATA)
  72. #define HC_HSTST_MASK_ERROR_ALL (HC_HSTST_MASK_ERROR_DATA | \
  73. HC_HSTST_TIMEOUT_CMD)
  74. /* Flags for HC_HOSTCONFIG register */
  75. #define HC_HSTCF_INTBUS_WIDE 0x0002
  76. #define HC_HSTCF_EXTBUS_4BIT 0x0004
  77. #define HC_HSTCF_SLOW_CARD 0x0008
  78. #define HC_HSTCF_INT_DATA 0x0010
  79. #define HC_HSTCF_INT_BLOCK 0x0100
  80. #define HC_HSTCF_INT_BUSY 0x0400
  81. /* Flags for HC_DEBUG register */
  82. #define HC_DBG_FIFO_THRESH_WRITE_SHIFT 9
  83. #define HC_DBG_FIFO_THRESH_READ_SHIFT 14
  84. #define HC_DBG_FIFO_THRESH_MASK 0x001f
  85. #define HC_DBG_FSM_MASK 0xf
  86. #define HC_DBG_FSM_IDENTMODE 0x0
  87. #define HC_DBG_FSM_DATAMODE 0x1
  88. #define HC_DBG_FSM_READDATA 0x2
  89. #define HC_DBG_FSM_WRITEDATA 0x3
  90. #define HC_DBG_FSM_READWAIT 0x4
  91. #define HC_DBG_FSM_READCRC 0x5
  92. #define HC_DBG_FSM_WRITECRC 0x6
  93. #define HC_DBG_FSM_WRITEWAIT1 0x7
  94. #define HC_DBG_FSM_POWERDOWN 0x8
  95. #define HC_DBG_FSM_POWERUP 0x9
  96. #define HC_DBG_FSM_WRITESTART1 0xa
  97. #define HC_DBG_FSM_WRITESTART2 0xb
  98. #define HC_DBG_FSM_GENPULSES 0xc
  99. #define HC_DBG_FSM_WRITEWAIT2 0xd
  100. #define HC_DBG_FSM_STARTPOWDOWN 0xf
  101. #define HC_DBG_FORCE_DATA_MODE 0x40000
  102. /* Settings */
  103. #define HC_FIFO_SIZE 16
  104. #define HC_FIFO_THRESH_READ 4
  105. #define HC_FIFO_THRESH_WRITE 4
  106. #define HC_TIMEOUT_DEFAULT 0x00f00000
  107. #define HC_TIMEOUT_IDLE 0x00a00000
  108. #endif /* RPI3_SDHOST_H */