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include
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drivers
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st
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stm32mp2_ddr.h

stm32mp2_ddr.h 2.9 KB
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  1. /*
    2. 

  2.  * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef STM32MP2_DDR_H
    8. 

  8. #define STM32MP2_DDR_H
    9. 

  9. 

  10. #include <stdbool.h>
    11. 

  11. 

  12. #include <ddrphy_phyinit_struct.h>
    13. 

  13. 

  14. #include <drivers/st/stm32mp_ddr.h>
    15. 

  15. 

  16. struct stm32mp2_ddrctrl_reg {
    17. 

  17. 	uint32_t mstr;
    18. 

  18. 	uint32_t mrctrl0;
    19. 

  19. 	uint32_t mrctrl1;
    20. 

  20. 	uint32_t mrctrl2;
    21. 

  21. 	uint32_t derateen;
    22. 

  22. 	uint32_t derateint;
    23. 

  23. 	uint32_t deratectl;
    24. 

  24. 	uint32_t pwrctl;
    25. 

  25. 	uint32_t pwrtmg;
    26. 

  26. 	uint32_t hwlpctl;
    27. 

  27. 	uint32_t rfshctl0;
    28. 

  28. 	uint32_t rfshctl1;
    29. 

  29. 	uint32_t rfshctl3;
    30. 

  30. 	uint32_t crcparctl0;
    31. 

  31. 	uint32_t crcparctl1;
    32. 

  32. 	uint32_t init0;
    33. 

  33. 	uint32_t init1;
    34. 

  34. 	uint32_t init2;
    35. 

  35. 	uint32_t init3;
    36. 

  36. 	uint32_t init4;
    37. 

  37. 	uint32_t init5;
    38. 

  38. 	uint32_t init6;
    39. 

  39. 	uint32_t init7;
    40. 

  40. 	uint32_t dimmctl;
    41. 

  41. 	uint32_t rankctl;
    42. 

  42. 	uint32_t rankctl1;
    43. 

  43. 	uint32_t zqctl0;
    44. 

  44. 	uint32_t zqctl1;
    45. 

  45. 	uint32_t zqctl2;
    46. 

  46. 	uint32_t dfitmg0;
    47. 

  47. 	uint32_t dfitmg1;
    48. 

  48. 	uint32_t dfilpcfg0;
    49. 

  49. 	uint32_t dfilpcfg1;
    50. 

  50. 	uint32_t dfiupd0;
    51. 

  51. 	uint32_t dfiupd1;
    52. 

  52. 	uint32_t dfiupd2;
    53. 

  53. 	uint32_t dfimisc;
    54. 

  54. 	uint32_t dfitmg2;
    55. 

  55. 	uint32_t dfitmg3;
    56. 

  56. 	uint32_t dbictl;
    57. 

  57. 	uint32_t dfiphymstr;
    58. 

  58. 	uint32_t dbg0;
    59. 

  59. 	uint32_t dbg1;
    60. 

  60. 	uint32_t dbgcmd;
    61. 

  61. 	uint32_t swctl;
    62. 

  62. 	uint32_t swctlstatic;
    63. 

  63. 	uint32_t poisoncfg;
    64. 

  64. 	uint32_t pccfg;
    65. 

  65. };
    66. 

  66. 

  67. struct stm32mp2_ddrctrl_timing {
    68. 

  68. 	uint32_t rfshtmg;
    69. 

  69. 	uint32_t rfshtmg1;
    70. 

  70. 	uint32_t dramtmg0;
    71. 

  71. 	uint32_t dramtmg1;
    72. 

  72. 	uint32_t dramtmg2;
    73. 

  73. 	uint32_t dramtmg3;
    74. 

  74. 	uint32_t dramtmg4;
    75. 

  75. 	uint32_t dramtmg5;
    76. 

  76. 	uint32_t dramtmg6;
    77. 

  77. 	uint32_t dramtmg7;
    78. 

  78. 	uint32_t dramtmg8;
    79. 

  79. 	uint32_t dramtmg9;
    80. 

  80. 	uint32_t dramtmg10;
    81. 

  81. 	uint32_t dramtmg11;
    82. 

  82. 	uint32_t dramtmg12;
    83. 

  83. 	uint32_t dramtmg13;
    84. 

  84. 	uint32_t dramtmg14;
    85. 

  85. 	uint32_t dramtmg15;
    86. 

  86. 	uint32_t odtcfg;
    87. 

  87. 	uint32_t odtmap;
    88. 

  88. };
    89. 

  89. 

  90. struct stm32mp2_ddrctrl_map {
    91. 

  91. 	uint32_t addrmap0;
    92. 

  92. 	uint32_t addrmap1;
    93. 

  93. 	uint32_t addrmap2;
    94. 

  94. 	uint32_t addrmap3;
    95. 

  95. 	uint32_t addrmap4;
    96. 

  96. 	uint32_t addrmap5;
    97. 

  97. 	uint32_t addrmap6;
    98. 

  98. 	uint32_t addrmap7;
    99. 

  99. 	uint32_t addrmap8;
    100. 

  100. 	uint32_t addrmap9;
    101. 

  101. 	uint32_t addrmap10;
    102. 

  102. 	uint32_t addrmap11;
    103. 

  103. };
    104. 

  104. 

  105. struct stm32mp2_ddrctrl_perf {
    106. 

  106. 	uint32_t sched;
    107. 

  107. 	uint32_t sched1;
    108. 

  108. 	uint32_t perfhpr1;
    109. 

  109. 	uint32_t perflpr1;
    110. 

  110. 	uint32_t perfwr1;
    111. 

  111. 	uint32_t sched3;
    112. 

  112. 	uint32_t sched4;
    113. 

  113. 	uint32_t pcfgr_0;
    114. 

  114. 	uint32_t pcfgw_0;
    115. 

  115. 	uint32_t pctrl_0;
    116. 

  116. 	uint32_t pcfgqos0_0;
    117. 

  117. 	uint32_t pcfgqos1_0;
    118. 

  118. 	uint32_t pcfgwqos0_0;
    119. 

  119. 	uint32_t pcfgwqos1_0;
    120. 

  120. #if STM32MP_DDR_DUAL_AXI_PORT
    121. 

  121. 	uint32_t pcfgr_1;
    122. 

  122. 	uint32_t pcfgw_1;
    123. 

  123. 	uint32_t pctrl_1;
    124. 

  124. 	uint32_t pcfgqos0_1;
    125. 

  125. 	uint32_t pcfgqos1_1;
    126. 

  126. 	uint32_t pcfgwqos0_1;
    127. 

  127. 	uint32_t pcfgwqos1_1;
    128. 

  128. #endif /* STM32MP_DDR_DUAL_AXI_PORT */
    129. 

  129. };
    130. 

  130. 

  131. struct stm32mp_ddr_config {
    132. 

  132. 	struct stm32mp_ddr_info info;
    133. 

  133. 	struct stm32mp2_ddrctrl_reg c_reg;
    134. 

  134. 	struct stm32mp2_ddrctrl_timing c_timing;
    135. 

  135. 	struct stm32mp2_ddrctrl_map c_map;
    136. 

  136. 	struct stm32mp2_ddrctrl_perf c_perf;
    137. 

  137. 	bool self_refresh;
    138. 

  138. 	uint32_t zdata;
    139. 

  139. 	struct user_input_basic uib;
    140. 

  140. 	struct user_input_advanced uia;
    141. 

  141. 	struct user_input_mode_register uim;
    142. 

  142. 	struct user_input_swizzle uis;
    143. 

  143. };
    144. 

  144. 

  145. void stm32mp2_ddr_init(struct stm32mp_ddr_priv *priv, struct stm32mp_ddr_config *config);
    146. 

  146. 

  147. #endif /* STM32MP2_DDR_H */
    148.