fvp-foundation-gicv2-psci.dts 3.1 KB

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  1. /*
  2. * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. /* Configuration: 1 cluster with up to 4 CPUs */
  7. /dts-v1/;
  8. #define AFF
  9. #define CLUSTER_COUNT 1
  10. #include <dt-bindings/interrupt-controller/arm-gic.h>
  11. #include "fvp-defs.dtsi"
  12. /memreserve/ 0x80000000 0x00010000;
  13. / {
  14. };
  15. / {
  16. model = "FVP Foundation";
  17. compatible = "arm,fvp-base", "arm,vexpress";
  18. interrupt-parent = <&gic>;
  19. #address-cells = <2>;
  20. #size-cells = <2>;
  21. chosen { };
  22. aliases {
  23. serial0 = &v2m_serial0;
  24. serial1 = &v2m_serial1;
  25. serial2 = &v2m_serial2;
  26. serial3 = &v2m_serial3;
  27. };
  28. psci {
  29. compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
  30. method = "smc";
  31. cpu_suspend = <0xc4000001>;
  32. cpu_off = <0x84000002>;
  33. cpu_on = <0xc4000003>;
  34. sys_poweroff = <0x84000008>;
  35. sys_reset = <0x84000009>;
  36. max-pwr-lvl = <2>;
  37. };
  38. cpus {
  39. #address-cells = <2>;
  40. #size-cells = <0>;
  41. CPU_MAP
  42. idle-states {
  43. entry-method = "arm,psci";
  44. CPU_SLEEP_0: cpu-sleep-0 {
  45. compatible = "arm,idle-state";
  46. local-timer-stop;
  47. arm,psci-suspend-param = <0x0010000>;
  48. entry-latency-us = <40>;
  49. exit-latency-us = <100>;
  50. min-residency-us = <150>;
  51. };
  52. CLUSTER_SLEEP_0: cluster-sleep-0 {
  53. compatible = "arm,idle-state";
  54. local-timer-stop;
  55. arm,psci-suspend-param = <0x1010000>;
  56. entry-latency-us = <500>;
  57. exit-latency-us = <1000>;
  58. min-residency-us = <2500>;
  59. };
  60. };
  61. CPUS
  62. L2_0: l2-cache0 {
  63. compatible = "cache";
  64. };
  65. };
  66. memory@80000000 {
  67. device_type = "memory";
  68. reg = <0x00000000 0x80000000 0 0x7F000000>,
  69. <0x00000008 0x80000000 0 0x80000000>;
  70. };
  71. gic: interrupt-controller@2f000000 {
  72. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  73. #interrupt-cells = <3>;
  74. #address-cells = <0>;
  75. interrupt-controller;
  76. reg = <0x0 0x2f000000 0 0x10000>,
  77. <0x0 0x2c000000 0 0x2000>,
  78. <0x0 0x2c010000 0 0x2000>,
  79. <0x0 0x2c02F000 0 0x2000>;
  80. interrupts = <1 9 0xf04>;
  81. };
  82. timer {
  83. compatible = "arm,armv8-timer";
  84. interrupts = <GIC_PPI 13
  85. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  86. <GIC_PPI 14
  87. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  88. <GIC_PPI 11
  89. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  90. <GIC_PPI 10
  91. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
  92. clock-frequency = <100000000>;
  93. };
  94. timer@2a810000 {
  95. compatible = "arm,armv7-timer-mem";
  96. reg = <0x0 0x2a810000 0x0 0x10000>;
  97. clock-frequency = <100000000>;
  98. #address-cells = <2>;
  99. #size-cells = <2>;
  100. ranges;
  101. frame@2a830000 {
  102. frame-number = <1>;
  103. interrupts = <0 26 4>;
  104. reg = <0x0 0x2a830000 0x0 0x10000>;
  105. };
  106. };
  107. pmu {
  108. compatible = "arm,armv8-pmuv3";
  109. interrupts = <0 60 4>,
  110. <0 61 4>,
  111. <0 62 4>,
  112. <0 63 4>;
  113. };
  114. smb {
  115. compatible = "simple-bus";
  116. #address-cells = <2>;
  117. #size-cells = <1>;
  118. ranges = <0 0 0 0x08000000 0x04000000>,
  119. <1 0 0 0x14000000 0x04000000>,
  120. <2 0 0 0x18000000 0x04000000>,
  121. <3 0 0 0x1c000000 0x04000000>,
  122. <4 0 0 0x0c000000 0x04000000>,
  123. <5 0 0 0x10000000 0x04000000>;
  124. #include "fvp-foundation-motherboard.dtsi"
  125. };
  126. };