stm32mp135f-dk.dts 6.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
  4. * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  5. */
  6. /dts-v1/;
  7. #include <dt-bindings/clock/stm32mp13-clksrc.h>
  8. #include "stm32mp135.dtsi"
  9. #include "stm32mp13xf.dtsi"
  10. #include "stm32mp13-ddr3-1x4Gb-1066-binF.dtsi"
  11. #include "stm32mp13-pinctrl.dtsi"
  12. / {
  13. model = "STMicroelectronics STM32MP135F-DK Discovery Board";
  14. compatible = "st,stm32mp135f-dk", "st,stm32mp135";
  15. aliases {
  16. serial0 = &uart4;
  17. serial1 = &usart1;
  18. serial2 = &uart8;
  19. serial3 = &usart2;
  20. };
  21. chosen {
  22. stdout-path = "serial0:115200n8";
  23. };
  24. memory@c0000000 {
  25. device_type = "memory";
  26. reg = <0xc0000000 0x20000000>;
  27. };
  28. vin: vin {
  29. compatible = "regulator-fixed";
  30. regulator-name = "vin";
  31. regulator-min-microvolt = <5000000>;
  32. regulator-max-microvolt = <5000000>;
  33. regulator-always-on;
  34. };
  35. v3v3_ao: v3v3_ao {
  36. compatible = "regulator-fixed";
  37. regulator-name = "v3v3_ao";
  38. regulator-min-microvolt = <3300000>;
  39. regulator-max-microvolt = <3300000>;
  40. regulator-always-on;
  41. };
  42. };
  43. &bsec {
  44. board_id: board_id@f0 {
  45. reg = <0xf0 0x4>;
  46. st,non-secure-otp;
  47. };
  48. };
  49. &cpu0 {
  50. cpu-supply = <&vddcpu>;
  51. };
  52. &hash {
  53. status = "okay";
  54. };
  55. &i2c4 {
  56. pinctrl-names = "default";
  57. pinctrl-0 = <&i2c4_pins_a>;
  58. i2c-scl-rising-time-ns = <185>;
  59. i2c-scl-falling-time-ns = <20>;
  60. clock-frequency = <400000>;
  61. status = "disabled";
  62. secure-status = "okay";
  63. pmic: stpmic@33 {
  64. compatible = "st,stpmic1";
  65. reg = <0x33>;
  66. status = "disabled";
  67. secure-status = "okay";
  68. regulators {
  69. compatible = "st,stpmic1-regulators";
  70. buck1-supply = <&vin>;
  71. buck2-supply = <&vin>;
  72. buck3-supply = <&vin>;
  73. buck4-supply = <&vin>;
  74. ldo1-supply = <&vin>;
  75. ldo4-supply = <&vin>;
  76. ldo5-supply = <&vin>;
  77. ldo6-supply = <&vin>;
  78. vref_ddr-supply = <&vin>;
  79. pwr_sw1-supply = <&bst_out>;
  80. pwr_sw2-supply = <&v3v3_ao>;
  81. vddcpu: buck1 {
  82. regulator-name = "vddcpu";
  83. regulator-min-microvolt = <1250000>;
  84. regulator-max-microvolt = <1250000>;
  85. regulator-always-on;
  86. regulator-over-current-protection;
  87. };
  88. vdd_ddr: buck2 {
  89. regulator-name = "vdd_ddr";
  90. regulator-min-microvolt = <1350000>;
  91. regulator-max-microvolt = <1350000>;
  92. regulator-always-on;
  93. regulator-over-current-protection;
  94. };
  95. vdd: buck3 {
  96. regulator-name = "vdd";
  97. regulator-min-microvolt = <3300000>;
  98. regulator-max-microvolt = <3300000>;
  99. regulator-always-on;
  100. st,mask-reset;
  101. regulator-over-current-protection;
  102. };
  103. vddcore: buck4 {
  104. regulator-name = "vddcore";
  105. regulator-min-microvolt = <1250000>;
  106. regulator-max-microvolt = <1250000>;
  107. regulator-always-on;
  108. regulator-over-current-protection;
  109. };
  110. vdd_adc: ldo1 {
  111. regulator-name = "vdd_adc";
  112. regulator-min-microvolt = <3300000>;
  113. regulator-max-microvolt = <3300000>;
  114. };
  115. vdd_usb: ldo4 {
  116. regulator-name = "vdd_usb";
  117. regulator-min-microvolt = <3300000>;
  118. regulator-max-microvolt = <3300000>;
  119. };
  120. vdd_sd: ldo5 {
  121. regulator-name = "vdd_sd";
  122. regulator-min-microvolt = <3300000>;
  123. regulator-max-microvolt = <3300000>;
  124. regulator-boot-on;
  125. };
  126. v1v8_periph: ldo6 {
  127. regulator-name = "v1v8_periph";
  128. regulator-min-microvolt = <1800000>;
  129. regulator-max-microvolt = <1800000>;
  130. };
  131. vref_ddr: vref_ddr {
  132. regulator-name = "vref_ddr";
  133. regulator-always-on;
  134. };
  135. bst_out: boost {
  136. regulator-name = "bst_out";
  137. };
  138. v3v3_sw: pwr_sw2 {
  139. regulator-name = "v3v3_sw";
  140. regulator-active-discharge = <1>;
  141. regulator-always-on;
  142. };
  143. };
  144. };
  145. };
  146. &iwdg2 {
  147. timeout-sec = <32>;
  148. status = "okay";
  149. };
  150. &pka {
  151. status = "okay";
  152. };
  153. &pwr_regulators {
  154. vdd-supply = <&vdd>;
  155. vdd_3v3_usbfs-supply = <&vdd_usb>;
  156. };
  157. &rcc {
  158. st,clksrc = <
  159. CLK_MPU_PLL1P
  160. CLK_AXI_PLL2P
  161. CLK_MLAHBS_PLL3
  162. CLK_CKPER_HSE
  163. CLK_RTC_LSE
  164. CLK_SDMMC1_PLL4P
  165. CLK_SDMMC2_PLL4P
  166. CLK_STGEN_HSE
  167. CLK_USBPHY_HSE
  168. CLK_I2C4_HSI
  169. CLK_USBO_USBPHY
  170. CLK_I2C12_HSI
  171. CLK_UART2_HSI
  172. CLK_UART4_HSI
  173. CLK_SAES_AXI
  174. >;
  175. st,clkdiv = <
  176. DIV(DIV_AXI, 0)
  177. DIV(DIV_MLAHB, 0)
  178. DIV(DIV_APB1, 1)
  179. DIV(DIV_APB2, 1)
  180. DIV(DIV_APB3, 1)
  181. DIV(DIV_APB4, 1)
  182. DIV(DIV_APB5, 2)
  183. DIV(DIV_APB6, 1)
  184. DIV(DIV_RTC, 0)
  185. >;
  186. st,pll_vco {
  187. pll1_vco_1300Mhz: pll1-vco-1300Mhz {
  188. src = < CLK_PLL12_HSE >;
  189. divmn = < 2 80 >;
  190. frac = < 0x800 >;
  191. };
  192. pll2_vco_1066Mhz: pll2-vco-1066Mhz {
  193. src = < CLK_PLL12_HSE >;
  194. divmn = < 2 65 >;
  195. frac = < 0x1400 >;
  196. };
  197. pll3_vco_417_8Mhz: pll3-vco-417_8Mhz {
  198. src = < CLK_PLL3_HSE >;
  199. divmn = < 1 33 >;
  200. frac = < 0x1a04 >;
  201. };
  202. pll4_vco_600Mhz: pll4-vco-600Mhz {
  203. src = < CLK_PLL4_HSE >;
  204. divmn = < 1 49 >;
  205. };
  206. };
  207. /* VCO = 1300.0 MHz => P = 650 (CPU) */
  208. pll1:st,pll@0 {
  209. compatible = "st,stm32mp1-pll";
  210. reg = <0>;
  211. st,pll = < &pll1_cfg1 >;
  212. pll1_cfg1: pll1_cfg1 {
  213. st,pll_vco = < &pll1_vco_1300Mhz >;
  214. st,pll_div_pqr = < 0 1 1 >;
  215. };
  216. };
  217. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
  218. pll2:st,pll@1 {
  219. compatible = "st,stm32mp1-pll";
  220. reg = <1>;
  221. st,pll = < &pll2_cfg1 >;
  222. pll2_cfg1: pll2_cfg1 {
  223. st,pll_vco = < &pll2_vco_1066Mhz >;
  224. st,pll_div_pqr = < 1 1 0 >;
  225. };
  226. };
  227. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 209 */
  228. pll3:st,pll@2 {
  229. compatible = "st,stm32mp1-pll";
  230. reg = <2>;
  231. st,pll = < &pll3_cfg1 >;
  232. pll3_cfg1: pll3_cfg1 {
  233. st,pll_vco = < &pll3_vco_417_8Mhz >;
  234. st,pll_div_pqr = < 1 16 1 >;
  235. };
  236. };
  237. /* VCO = 600.0 MHz => P = 50, Q = 10, R = 100 */
  238. pll4:st,pll@3 {
  239. compatible = "st,stm32mp1-pll";
  240. reg = <3>;
  241. st,pll = < &pll4_cfg1 >;
  242. pll4_cfg1: pll4_cfg1 {
  243. st,pll_vco = < &pll4_vco_600Mhz >;
  244. st,pll_div_pqr = < 11 59 5 >;
  245. };
  246. };
  247. };
  248. &rng {
  249. status = "okay";
  250. };
  251. &saes {
  252. status = "okay";
  253. };
  254. &sdmmc1 {
  255. pinctrl-names = "default";
  256. pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
  257. disable-wp;
  258. st,neg-edge;
  259. bus-width = <4>;
  260. vmmc-supply = <&vdd_sd>;
  261. status = "okay";
  262. };
  263. &uart4 {
  264. pinctrl-names = "default";
  265. pinctrl-0 = <&uart4_pins_a>;
  266. status = "okay";
  267. };
  268. &uart8 {
  269. pinctrl-names = "default";
  270. pinctrl-0 = <&uart8_pins_a>;
  271. status = "disabled";
  272. };
  273. &usart1 {
  274. pinctrl-names = "default";
  275. pinctrl-0 = <&usart1_pins_a>;
  276. uart-has-rtscts;
  277. status = "disabled";
  278. };