stm32mp15xx-dkx.dtsi 6.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
  4. * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
  5. */
  6. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  7. #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
  8. / {
  9. memory@c0000000 {
  10. device_type = "memory";
  11. reg = <0xc0000000 0x20000000>;
  12. };
  13. vin: vin {
  14. compatible = "regulator-fixed";
  15. regulator-name = "vin";
  16. regulator-min-microvolt = <5000000>;
  17. regulator-max-microvolt = <5000000>;
  18. regulator-always-on;
  19. };
  20. };
  21. &bsec {
  22. board_id: board_id@ec {
  23. reg = <0xec 0x4>;
  24. st,non-secure-otp;
  25. };
  26. };
  27. &clk_hse {
  28. st,digbypass;
  29. };
  30. &cpu0 {
  31. cpu-supply = <&vddcore>;
  32. };
  33. &cpu1 {
  34. cpu-supply = <&vddcore>;
  35. };
  36. &hash1 {
  37. status = "okay";
  38. };
  39. &i2c4 {
  40. pinctrl-names = "default";
  41. pinctrl-0 = <&i2c4_pins_a>;
  42. i2c-scl-rising-time-ns = <185>;
  43. i2c-scl-falling-time-ns = <20>;
  44. clock-frequency = <400000>;
  45. status = "okay";
  46. pmic: stpmic@33 {
  47. compatible = "st,stpmic1";
  48. reg = <0x33>;
  49. interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
  50. interrupt-controller;
  51. #interrupt-cells = <2>;
  52. status = "okay";
  53. regulators {
  54. compatible = "st,stpmic1-regulators";
  55. buck1-supply = <&vin>;
  56. buck2-supply = <&vin>;
  57. buck3-supply = <&vin>;
  58. buck4-supply = <&vin>;
  59. ldo1-supply = <&v3v3>;
  60. ldo2-supply = <&vin>;
  61. ldo3-supply = <&vdd_ddr>;
  62. ldo4-supply = <&vin>;
  63. ldo5-supply = <&vin>;
  64. ldo6-supply = <&v3v3>;
  65. vref_ddr-supply = <&vin>;
  66. boost-supply = <&vin>;
  67. pwr_sw1-supply = <&bst_out>;
  68. pwr_sw2-supply = <&bst_out>;
  69. vddcore: buck1 {
  70. regulator-name = "vddcore";
  71. regulator-min-microvolt = <1200000>;
  72. regulator-max-microvolt = <1350000>;
  73. regulator-always-on;
  74. regulator-initial-mode = <0>;
  75. regulator-over-current-protection;
  76. };
  77. vdd_ddr: buck2 {
  78. regulator-name = "vdd_ddr";
  79. regulator-min-microvolt = <1350000>;
  80. regulator-max-microvolt = <1350000>;
  81. regulator-always-on;
  82. regulator-initial-mode = <0>;
  83. regulator-over-current-protection;
  84. };
  85. vdd: buck3 {
  86. regulator-name = "vdd";
  87. regulator-min-microvolt = <3300000>;
  88. regulator-max-microvolt = <3300000>;
  89. regulator-always-on;
  90. st,mask-reset;
  91. regulator-initial-mode = <0>;
  92. regulator-over-current-protection;
  93. };
  94. v3v3: buck4 {
  95. regulator-name = "v3v3";
  96. regulator-min-microvolt = <3300000>;
  97. regulator-max-microvolt = <3300000>;
  98. regulator-always-on;
  99. regulator-over-current-protection;
  100. regulator-initial-mode = <0>;
  101. };
  102. v1v8_audio: ldo1 {
  103. regulator-name = "v1v8_audio";
  104. regulator-min-microvolt = <1800000>;
  105. regulator-max-microvolt = <1800000>;
  106. regulator-always-on;
  107. };
  108. v3v3_hdmi: ldo2 {
  109. regulator-name = "v3v3_hdmi";
  110. regulator-min-microvolt = <3300000>;
  111. regulator-max-microvolt = <3300000>;
  112. regulator-always-on;
  113. };
  114. vtt_ddr: ldo3 {
  115. regulator-name = "vtt_ddr";
  116. regulator-always-on;
  117. regulator-over-current-protection;
  118. st,regulator-sink-source;
  119. };
  120. vdd_usb: ldo4 {
  121. regulator-name = "vdd_usb";
  122. regulator-min-microvolt = <3300000>;
  123. regulator-max-microvolt = <3300000>;
  124. };
  125. vdda: ldo5 {
  126. regulator-name = "vdda";
  127. regulator-min-microvolt = <2900000>;
  128. regulator-max-microvolt = <2900000>;
  129. regulator-boot-on;
  130. };
  131. v1v2_hdmi: ldo6 {
  132. regulator-name = "v1v2_hdmi";
  133. regulator-min-microvolt = <1200000>;
  134. regulator-max-microvolt = <1200000>;
  135. regulator-always-on;
  136. };
  137. vref_ddr: vref_ddr {
  138. regulator-name = "vref_ddr";
  139. regulator-always-on;
  140. };
  141. bst_out: boost {
  142. regulator-name = "bst_out";
  143. };
  144. vbus_otg: pwr_sw1 {
  145. regulator-name = "vbus_otg";
  146. };
  147. vbus_sw: pwr_sw2 {
  148. regulator-name = "vbus_sw";
  149. regulator-active-discharge = <1>;
  150. };
  151. };
  152. };
  153. };
  154. &iwdg2 {
  155. timeout-sec = <32>;
  156. status = "okay";
  157. };
  158. &pwr_regulators {
  159. vdd-supply = <&vdd>;
  160. vdd_3v3_usbfs-supply = <&vdd_usb>;
  161. };
  162. &rcc {
  163. st,clksrc = <
  164. CLK_MPU_PLL1P
  165. CLK_AXI_PLL2P
  166. CLK_MCU_PLL3P
  167. CLK_PLL12_HSE
  168. CLK_PLL3_HSE
  169. CLK_PLL4_HSE
  170. CLK_RTC_LSE
  171. CLK_MCO1_DISABLED
  172. CLK_MCO2_DISABLED
  173. >;
  174. st,clkdiv = <
  175. 1 /*MPU*/
  176. 0 /*AXI*/
  177. 0 /*MCU*/
  178. 1 /*APB1*/
  179. 1 /*APB2*/
  180. 1 /*APB3*/
  181. 1 /*APB4*/
  182. 2 /*APB5*/
  183. 23 /*RTC*/
  184. 0 /*MCO1*/
  185. 0 /*MCO2*/
  186. >;
  187. st,pkcs = <
  188. CLK_CKPER_HSE
  189. CLK_FMC_ACLK
  190. CLK_QSPI_ACLK
  191. CLK_ETH_PLL4P
  192. CLK_SDMMC12_PLL4P
  193. CLK_DSI_DSIPLL
  194. CLK_STGEN_HSE
  195. CLK_USBPHY_HSE
  196. CLK_SPI2S1_PLL3Q
  197. CLK_SPI2S23_PLL3Q
  198. CLK_SPI45_HSI
  199. CLK_SPI6_HSI
  200. CLK_I2C46_HSI
  201. CLK_SDMMC3_PLL4P
  202. CLK_USBO_USBPHY
  203. CLK_ADC_CKPER
  204. CLK_CEC_LSE
  205. CLK_I2C12_HSI
  206. CLK_I2C35_HSI
  207. CLK_UART1_HSI
  208. CLK_UART24_HSI
  209. CLK_UART35_HSI
  210. CLK_UART6_HSI
  211. CLK_UART78_HSI
  212. CLK_SPDIF_PLL4P
  213. CLK_FDCAN_PLL4R
  214. CLK_SAI1_PLL3Q
  215. CLK_SAI2_PLL3Q
  216. CLK_SAI3_PLL3Q
  217. CLK_SAI4_PLL3Q
  218. CLK_RNG1_LSI
  219. CLK_RNG2_LSI
  220. CLK_LPTIM1_PCLK1
  221. CLK_LPTIM23_PCLK3
  222. CLK_LPTIM45_LSE
  223. >;
  224. /* VCO = 1300.0 MHz => P = 650 (CPU) */
  225. pll1: st,pll@0 {
  226. compatible = "st,stm32mp1-pll";
  227. reg = <0>;
  228. cfg = < 2 80 0 0 0 PQR(1,0,0) >;
  229. frac = < 0x800 >;
  230. };
  231. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  232. pll2: st,pll@1 {
  233. compatible = "st,stm32mp1-pll";
  234. reg = <1>;
  235. cfg = <2 65 1 0 0 PQR(1,1,1)>;
  236. frac = <0x1400>;
  237. };
  238. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  239. pll3: st,pll@2 {
  240. compatible = "st,stm32mp1-pll";
  241. reg = <2>;
  242. cfg = <1 33 1 16 36 PQR(1,1,1)>;
  243. frac = <0x1a04>;
  244. };
  245. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  246. pll4: st,pll@3 {
  247. compatible = "st,stm32mp1-pll";
  248. reg = <3>;
  249. cfg = <3 98 5 7 7 PQR(1,1,1)>;
  250. };
  251. };
  252. &rng1 {
  253. status = "okay";
  254. };
  255. &rtc {
  256. status = "okay";
  257. };
  258. &sdmmc1 {
  259. pinctrl-names = "default";
  260. pinctrl-0 = <&sdmmc1_b4_pins_a>;
  261. disable-wp;
  262. st,neg-edge;
  263. bus-width = <4>;
  264. vmmc-supply = <&v3v3>;
  265. status = "okay";
  266. };
  267. &uart4 {
  268. pinctrl-names = "default";
  269. pinctrl-0 = <&uart4_pins_a>;
  270. status = "okay";
  271. };
  272. &uart7 {
  273. pinctrl-names = "default";
  274. pinctrl-0 = <&uart7_pins_c>;
  275. status = "disabled";
  276. };
  277. &usart3 {
  278. pinctrl-names = "default";
  279. pinctrl-0 = <&usart3_pins_c>;
  280. uart-has-rtscts;
  281. status = "disabled";
  282. };
  283. &usbotg_hs {
  284. phys = <&usbphyc_port1 0>;
  285. phy-names = "usb2-phy";
  286. usb-role-switch;
  287. status = "okay";
  288. };
  289. &usbphyc {
  290. status = "okay";
  291. };
  292. &usbphyc_port0 {
  293. phy-supply = <&vdd_usb>;
  294. };
  295. &usbphyc_port1 {
  296. phy-supply = <&vdd_usb>;
  297. };