cortex_a78.h 2.2 KB

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  1. /*
  2. * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #ifndef CORTEX_A78_H
  7. #define CORTEX_A78_H
  8. #include <lib/utils_def.h>
  9. #define CORTEX_A78_MIDR U(0x410FD410)
  10. /* Cortex-A78 loop count for CVE-2022-23960 mitigation */
  11. #define CORTEX_A78_BHB_LOOP_COUNT U(32)
  12. /*******************************************************************************
  13. * CPU Extended Control register specific definitions.
  14. ******************************************************************************/
  15. #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
  16. #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
  17. #define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
  18. #define CPUECTLR_EL1_PF_MODE_LSB U(6)
  19. #define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
  20. /*******************************************************************************
  21. * CPU Power Control register specific definitions
  22. ******************************************************************************/
  23. #define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
  24. #define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
  25. /*******************************************************************************
  26. * CPU Auxiliary Control register specific definitions.
  27. ******************************************************************************/
  28. #define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
  29. #define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
  30. #define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0)
  31. #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
  32. #define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
  33. #define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
  34. #define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2
  35. #define CORTEX_A78_ACTLR5_EL1 S3_0_C15_C9_0
  36. /*******************************************************************************
  37. * CPU Activity Monitor Unit register specific definitions.
  38. ******************************************************************************/
  39. #define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
  40. #define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
  41. #define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
  42. #define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
  43. #define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
  44. #define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
  45. #endif /* CORTEX_A78_H */