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neoverse_n2.h

neoverse_n2.h 2.7 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef NEOVERSE_N2_H
    8. 

  8. #define NEOVERSE_N2_H
    9. 

  9. 

  10. /* Neoverse N2 ID register for revision r0p0 */
    11. 

  11. #define NEOVERSE_N2_MIDR				U(0x410FD490)
    12. 

  12. 

  13. /* Neoverse N2 loop count for CVE-2022-23960 mitigation */
    14. 

  14. #define NEOVERSE_N2_BHB_LOOP_COUNT			U(32)
    15. 

  15. 

  16. /*******************************************************************************
    17. 

  17.  * CPU Power control register
    18. 

  18.  ******************************************************************************/
    19. 

  19. #define NEOVERSE_N2_CPUPWRCTLR_EL1			S3_0_C15_C2_7
    20. 

  20. #define NEOVERSE_N2_CORE_PWRDN_EN_BIT			(ULL(1) << 0)
    21. 

  21. 

  22. /*******************************************************************************
    23. 

  23.  * CPU Extended Control register specific definitions.
    24. 

  24.  ******************************************************************************/
    25. 

  25. #define NEOVERSE_N2_CPUECTLR_EL1			S3_0_C15_C1_4
    26. 

  26. #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT		(ULL(1) << 0)
    27. 

  27. #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT		(ULL(1) << 8)
    28. 

  28. 

  29. /*******************************************************************************
    30. 

  30.  * CPU Auxiliary Control register specific definitions.
    31. 

  31.  ******************************************************************************/
    32. 

  32. #define NEOVERSE_N2_CPUACTLR_EL1			S3_0_C15_C1_0
    33. 

  33. #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46			(ULL(1) << 46)
    34. 

  34. #define NEOVERSE_N2_CPUACTLR_EL1_BIT_22			(ULL(1) << 22)
    35. 

  35. 

  36. /*******************************************************************************
    37. 

  37.  * CPU Auxiliary Control register 2 specific definitions.
    38. 

  38.  ******************************************************************************/
    39. 

  39. #define NEOVERSE_N2_CPUACTLR2_EL1			S3_0_C15_C1_1
    40. 

  40. #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0			(ULL(1) << 0)
    41. 

  41. #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2			(ULL(1) << 2)
    42. 

  42. #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36		(ULL(1) << 36)
    43. 

  43. #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40		(ULL(1) << 40)
    44. 

  44. 

  45. /*******************************************************************************
    46. 

  46.  * CPU Auxiliary Control register 5 specific definitions.
    47. 

  47.  ******************************************************************************/
    48. 

  48. #define NEOVERSE_N2_CPUACTLR5_EL1			S3_0_C15_C8_0
    49. 

  49. #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44		(ULL(1) << 44)
    50. 

  50. #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13		(ULL(1) << 13)
    51. 

  51. #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17		(ULL(1) << 17)
    52. 

  52. 

  53. /*******************************************************************************
    54. 

  54.  * CPU Auxiliary Control register specific definitions.
    55. 

  55.  ******************************************************************************/
    56. 

  56. #define NEOVERSE_N2_CPUECTLR2_EL1			S3_0_C15_C1_5
    57. 

  57. #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV		ULL(9)
    58. 

  58. #define CPUECTLR2_EL1_PF_MODE_LSB			U(11)
    59. 

  59. #define CPUECTLR2_EL1_PF_MODE_WIDTH			U(4)
    60. 

  60. 

  61. #endif /* NEOVERSE_N2_H */
    62.