cpu_ops.h 3.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105
  1. /*
  2. * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #ifndef CPU_OPS_H
  7. #define CPU_OPS_H
  8. #include <arch.h>
  9. #define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
  10. (MIDR_PN_MASK << MIDR_PN_SHIFT)
  11. /* Hardcode to keep compatible with assembly. sizeof(uintptr_t) */
  12. #if __aarch64__
  13. #define CPU_WORD_SIZE 8
  14. #else
  15. #define CPU_WORD_SIZE 4
  16. #endif /* __aarch64__ */
  17. /* The number of CPU operations allowed */
  18. #define CPU_MAX_PWR_DWN_OPS 2
  19. /* Special constant to specify that CPU has no reset function */
  20. #define CPU_NO_RESET_FUNC 0
  21. #if __aarch64__
  22. #define CPU_NO_EXTRA1_FUNC 0
  23. #define CPU_NO_EXTRA2_FUNC 0
  24. #define CPU_NO_EXTRA3_FUNC 0
  25. #endif /* __aarch64__ */
  26. /*
  27. * Define the sizes of the fields in the cpu_ops structure. Word size is set per
  28. * Aarch so keep these definitions the same and each can include whatever it
  29. * needs.
  30. */
  31. #define CPU_MIDR_SIZE CPU_WORD_SIZE
  32. #ifdef IMAGE_AT_EL3
  33. #define CPU_RESET_FUNC_SIZE CPU_WORD_SIZE
  34. #else
  35. #define CPU_RESET_FUNC_SIZE 0
  36. #endif /* IMAGE_AT_EL3 */
  37. #define CPU_EXTRA1_FUNC_SIZE CPU_WORD_SIZE
  38. #define CPU_EXTRA2_FUNC_SIZE CPU_WORD_SIZE
  39. #define CPU_EXTRA3_FUNC_SIZE CPU_WORD_SIZE
  40. #define CPU_E_HANDLER_FUNC_SIZE CPU_WORD_SIZE
  41. /* The power down core and cluster is needed only in BL31 and BL32 */
  42. #if defined(IMAGE_BL31) || defined(IMAGE_BL32)
  43. #define CPU_PWR_DWN_OPS_SIZE CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
  44. #else
  45. #define CPU_PWR_DWN_OPS_SIZE 0
  46. #endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */
  47. /* Fields required to print errata status */
  48. #if REPORT_ERRATA
  49. #define CPU_ERRATA_FUNC_SIZE CPU_WORD_SIZE
  50. /* BL1 doesn't require mutual exclusion and printed flag. */
  51. #if defined(IMAGE_BL31) || defined(IMAGE_BL32)
  52. #define CPU_ERRATA_LOCK_SIZE CPU_WORD_SIZE
  53. #define CPU_ERRATA_PRINTED_SIZE CPU_WORD_SIZE
  54. #else
  55. #define CPU_ERRATA_LOCK_SIZE 0
  56. #define CPU_ERRATA_PRINTED_SIZE 0
  57. #endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */
  58. #else
  59. #define CPU_ERRATA_FUNC_SIZE 0
  60. #define CPU_ERRATA_LOCK_SIZE 0
  61. #define CPU_ERRATA_PRINTED_SIZE 0
  62. #endif /* REPORT_ERRATA */
  63. #if defined(IMAGE_BL31) && CRASH_REPORTING
  64. #define CPU_REG_DUMP_SIZE CPU_WORD_SIZE
  65. #else
  66. #define CPU_REG_DUMP_SIZE 0
  67. #endif /* defined(IMAGE_BL31) && CRASH_REPORTING */
  68. /*
  69. * Define the offsets to the fields in cpu_ops structure. Every offset is
  70. * defined based on the offset and size of the previous field.
  71. */
  72. #define CPU_MIDR 0
  73. #define CPU_RESET_FUNC CPU_MIDR + CPU_MIDR_SIZE
  74. #if __aarch64__
  75. #define CPU_EXTRA1_FUNC CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
  76. #define CPU_EXTRA2_FUNC CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
  77. #define CPU_EXTRA3_FUNC CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
  78. #define CPU_E_HANDLER_FUNC CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE
  79. #define CPU_PWR_DWN_OPS CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
  80. #else
  81. #define CPU_PWR_DWN_OPS CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
  82. #endif /* __aarch64__ */
  83. #define CPU_ERRATA_FUNC CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
  84. #define CPU_ERRATA_LOCK CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
  85. #define CPU_ERRATA_PRINTED CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
  86. #if __aarch64__
  87. #define CPU_REG_DUMP CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
  88. #define CPU_OPS_SIZE CPU_REG_DUMP + CPU_REG_DUMP_SIZE
  89. #else
  90. #define CPU_OPS_SIZE CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
  91. #endif /* __aarch64__ */
  92. #endif /* CPU_OPS_H */