platform_common.c 2.4 KB

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  1. /*
  2. * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <platform_def.h>
  7. #include <arch_helpers.h>
  8. #include <common/bl_common.h>
  9. #include <common/debug.h>
  10. #include <drivers/arm/cci.h>
  11. #include <lib/utils.h>
  12. #include <lib/xlat_tables/xlat_tables.h>
  13. #include <mt8173_def.h>
  14. static const int cci_map[] = {
  15. PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX,
  16. PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX
  17. };
  18. /* Table of regions to map using the MMU. */
  19. const mmap_region_t plat_mmap[] = {
  20. /* for TF text, RO, RW */
  21. MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE,
  22. MT_MEMORY | MT_RW | MT_SECURE),
  23. MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
  24. MT_DEVICE | MT_RW | MT_SECURE),
  25. MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
  26. MT_DEVICE | MT_RW | MT_SECURE),
  27. { 0 }
  28. };
  29. /*******************************************************************************
  30. * Macro generating the code for the function setting up the pagetables as per
  31. * the platform memory map & initialize the mmu, for the given exception level
  32. ******************************************************************************/
  33. #define DEFINE_CONFIGURE_MMU_EL(_el) \
  34. void plat_configure_mmu_el ## _el(unsigned long total_base, \
  35. unsigned long total_size, \
  36. unsigned long ro_start, \
  37. unsigned long ro_limit, \
  38. unsigned long coh_start, \
  39. unsigned long coh_limit) \
  40. { \
  41. mmap_add_region(total_base, total_base, \
  42. total_size, \
  43. MT_MEMORY | MT_RW | MT_SECURE); \
  44. mmap_add_region(ro_start, ro_start, \
  45. ro_limit - ro_start, \
  46. MT_MEMORY | MT_RO | MT_SECURE); \
  47. mmap_add_region(coh_start, coh_start, \
  48. coh_limit - coh_start, \
  49. MT_DEVICE | MT_RW | MT_SECURE); \
  50. mmap_add(plat_mmap); \
  51. init_xlat_tables(); \
  52. \
  53. enable_mmu_el ## _el(0); \
  54. }
  55. /* Define EL3 variants of the function initialising the MMU */
  56. DEFINE_CONFIGURE_MMU_EL(3)
  57. unsigned int plat_get_syscnt_freq2(void)
  58. {
  59. return SYS_COUNTER_FREQ_IN_TICKS;
  60. }
  61. void plat_cci_init(void)
  62. {
  63. /* Initialize CCI driver */
  64. cci_init(PLAT_MT_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
  65. }
  66. void plat_cci_enable(void)
  67. {
  68. /*
  69. * Enable CCI coherency for this cluster.
  70. * No need for locks as no other cpu is active at the moment.
  71. */
  72. cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
  73. }
  74. void plat_cci_disable(void)
  75. {
  76. cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
  77. }