mt_spm_pmic_wrap.h 1.1 KB

123456789101112131415161718192021222324252627282930313233343536373839
  1. /*
  2. * Copyright (c) 2022, MediaTek Inc. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. /****************************************************************
  7. * Auto generated by DE, please DO NOT modify this file directly.
  8. *****************************************************************/
  9. #ifndef MT_SPM_PMIC_WRAP_H
  10. #define MT_SPM_PMIC_WRAP_H
  11. enum pmic_wrap_phase_id {
  12. PMIC_WRAP_PHASE_ALLINONE = 0U,
  13. NR_PMIC_WRAP_PHASE = 1U,
  14. };
  15. /* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
  16. enum {
  17. CMD_0 = 0U, /* 0x0 */
  18. CMD_1 = 1U, /* 0x1 */
  19. CMD_2 = 2U, /* 0x2 */
  20. CMD_3 = 3U, /* 0x3 */
  21. CMD_4 = 4U, /* 0x4 */
  22. CMD_5 = 5U, /* 0x5 */
  23. CMD_6 = 6U, /* 0x6 */
  24. CMD_7 = 7U, /* 0x7 */
  25. CMD_8 = 8U, /* 0x8 */
  26. NR_IDX_ALL = 9U,
  27. };
  28. /* APIs */
  29. extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
  30. extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
  31. uint32_t idx, uint32_t cmd_wdata);
  32. extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
  33. uint32_t idx);
  34. #endif /* MT_SPM_PMIC_WRAP_H */