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arm-trusted-firmware
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plat
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rockchip
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rk3399
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rk3399_def.h

rk3399_def.h 2.2 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef RK3399_DEF_H
    8. 

  8. #define RK3399_DEF_H
    9. 

  9. 

  10. #include <addressmap.h>
    11. 

  11. 

  12. #define RK3399_PRIMARY_CPU		0x0
    13. 

  13. 

  14. /* Special value used to verify platform parameters from BL2 to BL3-1 */
    15. 

  15. #define RK_BL31_PLAT_PARAM_VAL		0x0f1e2d3c4b5a6978ULL
    16. 

  16. 

  17. /**************************************************************************
    18. 

  18.  * UART related constants
    19. 

  19.  **************************************************************************/
    20. 

  20. #define RK3399_BAUDRATE			115200
    21. 

  21. #define RK3399_UART_CLOCK		24000000
    22. 

  22. 

  23. /******************************************************************************
    24. 

  24.  * System counter frequency related constants
    25. 

  25.  ******************************************************************************/
    26. 

  26. #define SYS_COUNTER_FREQ_IN_TICKS	24000000
    27. 

  27. 

  28. /* Base rockchip_platform compatible GIC memory map */
    29. 

  29. #define BASE_GICD_BASE			(GIC500_BASE)
    30. 

  30. #define BASE_GICR_BASE			(GIC500_BASE + SIZE_M(1))
    31. 

  31. 

  32. /*****************************************************************************
    33. 

  33.  * CCI-400 related constants
    34. 

  34.  ******************************************************************************/
    35. 

  35. #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX	0
    36. 

  36. #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX	1
    37. 

  37. 

  38. /******************************************************************************
    39. 

  39.  * sgi, ppi
    40. 

  40.  ******************************************************************************/
    41. 

  41. #define ARM_IRQ_SEC_PHY_TIMER		29
    42. 

  42. 

  43. #define ARM_IRQ_SEC_SGI_0		8
    44. 

  44. #define ARM_IRQ_SEC_SGI_1		9
    45. 

  45. #define ARM_IRQ_SEC_SGI_2		10
    46. 

  46. #define ARM_IRQ_SEC_SGI_3		11
    47. 

  47. #define ARM_IRQ_SEC_SGI_4		12
    48. 

  48. #define ARM_IRQ_SEC_SGI_5		13
    49. 

  49. #define ARM_IRQ_SEC_SGI_6		14
    50. 

  50. #define ARM_IRQ_SEC_SGI_7		15
    51. 

  51. 

  52. /*
    53. 

  53.  * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
    54. 

  54.  * terminology. On a GICv2 system or mode, the lists will be merged and treated
    55. 

  55.  * as Group 0 interrupts.
    56. 

  56.  */
    57. 

  57. #define PLAT_RK_GICV3_G1S_IRQS						\
    58. 

  58. 	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,	\
    59. 

  59. 		       INTR_GROUP1S, GIC_INTR_CFG_LEVEL)
    60. 

  60. 

  61. #define PLAT_RK_GICV3_G0_IRQS						\
    62. 

  62. 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,	\
    63. 

  63. 		       INTR_GROUP0, GIC_INTR_CFG_LEVEL)
    64. 

  64. 

  65. #endif /* RK3399_DEF_H */
    66.