phy-porting-layer.h 4.2 KB

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  1. /*
  2. * Copyright (C) 2018 Marvell International Ltd.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. * https://spdx.org/licenses
  6. */
  7. #ifndef __PHY_PORTING_LAYER_H
  8. #define __PHY_PORTING_LAYER_H
  9. #define MAX_LANE_NR 6
  10. #define XFI_PARAMS static const struct xfi_params
  11. XFI_PARAMS xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
  12. /* AP0 */
  13. {
  14. /* CP 0 */
  15. {
  16. { 0 }, /* Comphy0 not relevant*/
  17. { 0 }, /* Comphy1 not relevant*/
  18. { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
  19. .align90 = 0x5f,
  20. .g1_dfe_res = 0x2, .g1_amp = 0x1c,
  21. .g1_emph = 0xe,
  22. .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
  23. .g1_tx_emph_en = 0x1,
  24. .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
  25. .g1_rx_selmufi = 0x0,
  26. .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
  27. .valid = 1 }, /* Comphy2 */
  28. { 0 }, /* Comphy3 not relevant*/
  29. { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
  30. .align90 = 0x5f,
  31. .g1_dfe_res = 0x2, .g1_amp = 0x1c,
  32. .g1_emph = 0xe,
  33. .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
  34. .g1_tx_emph_en = 0x1,
  35. .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
  36. .g1_rx_selmufi = 0x0,
  37. .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
  38. .valid = 1 }, /* Comphy4 */
  39. { 0 }, /* Comphy5 not relevant*/
  40. },
  41. #if CP_NUM > 1
  42. /* CP 1 */
  43. {
  44. { 0 }, /* Comphy0 not relevant*/
  45. { 0 }, /* Comphy1 not relevant*/
  46. { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
  47. .align90 = 0x5f,
  48. .g1_dfe_res = 0x2, .g1_amp = 0x1c,
  49. .g1_emph = 0xe,
  50. .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
  51. .g1_tx_emph_en = 0x1,
  52. .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
  53. .g1_rx_selmufi = 0x0,
  54. .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
  55. .valid = 1 }, /* Comphy2 */
  56. { 0 }, /* Comphy3 not relevant*/
  57. /* different from defaults */
  58. { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
  59. .align90 = 0x5f,
  60. .g1_dfe_res = 0x2, .g1_amp = 0xc,
  61. .g1_emph = 0x5,
  62. .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
  63. .g1_tx_emph_en = 0x1,
  64. .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
  65. .g1_rx_selmufi = 0x0,
  66. .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
  67. .valid = 1}, /* Comphy4 */
  68. { 0 }, /* Comphy5 not relevant*/
  69. },
  70. #if CP_NUM > 2
  71. /* CP 2 */
  72. {
  73. { 0 }, /* Comphy0 not relevant*/
  74. { 0 }, /* Comphy1 not relevant*/
  75. { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
  76. .align90 = 0x5f,
  77. .g1_dfe_res = 0x2, .g1_amp = 0x1c,
  78. .g1_emph = 0xe,
  79. .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
  80. .g1_tx_emph_en = 0x1,
  81. .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
  82. .g1_rx_selmufi = 0x0,
  83. .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
  84. .valid = 1 }, /* Comphy2 */
  85. { 0 }, /* Comphy3 not relevant*/
  86. { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
  87. .align90 = 0x5f,
  88. .g1_dfe_res = 0x2, .g1_amp = 0x1c,
  89. .g1_emph = 0xe,
  90. .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
  91. .g1_tx_emph_en = 0x1,
  92. .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1,
  93. .g1_rx_selmufi = 0x0,
  94. .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
  95. .valid = 1 }, /* Comphy4 */
  96. { 0 }, /* Comphy5 not relevant*/
  97. },
  98. #endif
  99. #endif
  100. },
  101. };
  102. #define SATA_PARAMS static const struct sata_params
  103. SATA_PARAMS sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
  104. [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
  105. .g1_amp = 0x8, .g2_amp = 0xa,
  106. .g3_amp = 0x1e,
  107. .g1_emph = 0x1, .g2_emph = 0x2,
  108. .g3_emph = 0xe,
  109. .g1_emph_en = 0x1, .g2_emph_en = 0x1,
  110. .g3_emph_en = 0x1,
  111. .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
  112. .g3_tx_amp_adj = 0x1,
  113. .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
  114. .g3_tx_emph_en = 0x0,
  115. .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
  116. .g3_tx_emph = 0x1,
  117. .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
  118. .g3_ffe_cap_sel = 0xf,
  119. .align90 = 0x61,
  120. .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
  121. .g3_rx_selmuff = 0x3,
  122. .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
  123. .g3_rx_selmufi = 0x3,
  124. .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
  125. .g3_rx_selmupf = 0x2,
  126. .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
  127. .g3_rx_selmupi = 0x2,
  128. .polarity_invert = COMPHY_POLARITY_NO_INVERT,
  129. .valid = 0x1
  130. },
  131. };
  132. static const struct usb_params
  133. usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
  134. [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
  135. .polarity_invert = COMPHY_POLARITY_NO_INVERT
  136. },
  137. };
  138. #endif /* __PHY_PORTING_LAYER_H */