mt_spm_rc_syspll.c 9.5 KB

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  1. /*
  2. * Copyright (c) 2023, MediaTek Inc. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <assert.h>
  7. #include <common/debug.h>
  8. #include <drivers/spm/mt_spm_resource_req.h>
  9. #include <lib/pm/mtk_pm.h>
  10. #include <lpm/mt_lp_api.h>
  11. #include <lpm/mt_lp_rm.h>
  12. #include <mt_spm.h>
  13. #include <mt_spm_cond.h>
  14. #include <mt_spm_conservation.h>
  15. #include <mt_spm_constraint.h>
  16. #include <mt_spm_idle.h>
  17. #include <mt_spm_internal.h>
  18. #include <mt_spm_notifier.h>
  19. #include "mt_spm_rc_api.h"
  20. #include "mt_spm_rc_internal.h"
  21. #include <mt_spm_reg.h>
  22. #include <mt_spm_suspend.h>
  23. #define CONSTRAINT_SYSPLL_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
  24. MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
  25. MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
  26. MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
  27. #define CONSTRAINT_SYSPLL_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
  28. SPM_FLAG_DISABLE_VCORE_DVS | \
  29. SPM_FLAG_DISABLE_VCORE_DFS | \
  30. SPM_FLAG_SRAM_SLEEP_CTRL | \
  31. SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
  32. SPM_FLAG_ENABLE_6315_CTRL | \
  33. SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
  34. SPM_FLAG_USE_SRCCLKENO2)
  35. #define CONSTRAINT_SYSPLL_PCM_FLAG1 (0)
  36. /* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
  37. #if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
  38. #define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
  39. #else
  40. #define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
  41. #endif
  42. static unsigned int syspll_ext_opand2;
  43. static unsigned short ext_status_syspll;
  44. static struct mt_spm_cond_tables cond_syspll = {
  45. .name = "syspll",
  46. .table_cg = {
  47. 0xFF5DD002, /* MTCMOS1 */
  48. 0x0000003C, /* MTCMOS2 */
  49. 0x27AF8000, /* INFRA0 */
  50. 0x20010876, /* INFRA1 */
  51. 0x86000640, /* INFRA2 */
  52. 0x30008020, /* INFRA3 */
  53. 0x80000000, /* INFRA4 */
  54. 0x01002A0B, /* PERI0 */
  55. 0x00090000, /* VPPSYS0_0 */
  56. 0x38FF3E69, /* VPPSYS0_1 */
  57. 0xF0081450, /* VPPSYS1_0 */
  58. 0x00003000, /* VPPSYS1_1 */
  59. 0x00000000, /* VDOSYS0_0 */
  60. 0x00000000, /* VDOSYS0_1 */
  61. 0x000001FF, /* VDOSYS1_0 */
  62. 0x008001E0, /* VDOSYS1_1 */
  63. 0x00FB0007, /* VDOSYS1_2 */
  64. },
  65. .table_pll = 0U,
  66. };
  67. static struct mt_spm_cond_tables cond_syspll_res = {
  68. .table_cg = { 0U },
  69. .table_pll = 0U,
  70. };
  71. static struct constraint_status status = {
  72. .id = MT_RM_CONSTRAINT_ID_SYSPLL,
  73. .is_valid = (MT_SPM_RC_VALID_SW |
  74. MT_SPM_RC_VALID_COND_CHECK |
  75. MT_SPM_RC_VALID_COND_LATCH |
  76. MT_SPM_RC_VALID_XSOC_BBLPM |
  77. MT_SPM_RC_VALID_TRACE_TIME),
  78. .is_cond_block = 0U,
  79. .enter_cnt = 0U,
  80. .cond_res = &cond_syspll_res,
  81. .residency = 0ULL,
  82. };
  83. int spm_syspll_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
  84. {
  85. unsigned int res_req = CONSTRAINT_SYSPLL_RESOURCE_REQ;
  86. if ((spm_lp == NULL) || (resource_req == NULL)) {
  87. return -1;
  88. }
  89. spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
  90. spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
  91. *resource_req |= res_req;
  92. return 0;
  93. }
  94. bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
  95. {
  96. return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
  97. IS_MT_RM_RC_READY(status.is_valid) &&
  98. (IS_PLAT_SUSPEND_ID(state_id) ||
  99. (state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
  100. (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
  101. }
  102. static int update_rc_condition(int state_id, const void *val)
  103. {
  104. int res = MT_RM_STATUS_OK;
  105. const struct mt_spm_cond_tables * const tlb =
  106. (const struct mt_spm_cond_tables * const)val;
  107. const struct mt_spm_cond_tables *tlb_check =
  108. (const struct mt_spm_cond_tables *)&cond_syspll;
  109. if (tlb == NULL) {
  110. return MT_RM_STATUS_BAD;
  111. }
  112. status.is_cond_block = mt_spm_cond_check(state_id, tlb, tlb_check,
  113. (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
  114. &cond_syspll_res : NULL);
  115. return res;
  116. }
  117. static void update_rc_clkbuf_status(const void *val)
  118. {
  119. unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
  120. if (is_flight != 0U) {
  121. spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
  122. MT_RM_CONSTRAINT_ID_SYSPLL,
  123. MT_SPM_RC_VALID_FLIGHTMODE,
  124. (struct constraint_status * const)&status);
  125. } else {
  126. spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
  127. MT_RM_CONSTRAINT_ID_SYSPLL,
  128. MT_SPM_RC_VALID_FLIGHTMODE,
  129. (struct constraint_status * const)&status);
  130. }
  131. }
  132. static void update_rc_ufs_status(const void *val)
  133. {
  134. unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
  135. if (is_ufs_h8 != 0U) {
  136. spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
  137. MT_RM_CONSTRAINT_ID_SYSPLL,
  138. MT_SPM_RC_VALID_UFS_H8,
  139. (struct constraint_status * const)&status);
  140. } else {
  141. spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
  142. MT_RM_CONSTRAINT_ID_SYSPLL,
  143. MT_SPM_RC_VALID_UFS_H8,
  144. (struct constraint_status * const)&status);
  145. }
  146. }
  147. static void update_rc_usb_peri(const void *val)
  148. {
  149. int *flag = (int *)val;
  150. if (flag == NULL) {
  151. return;
  152. }
  153. if (*flag != 0) {
  154. SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
  155. } else {
  156. SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
  157. }
  158. }
  159. static void update_rc_usb_infra(const void *val)
  160. {
  161. int *flag = (int *)val;
  162. if (flag == NULL) {
  163. return;
  164. }
  165. if (*flag != 0) {
  166. SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
  167. } else {
  168. SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
  169. }
  170. }
  171. static void update_rc_status(const void *val)
  172. {
  173. const struct rc_common_state *st;
  174. st = (const struct rc_common_state *)val;
  175. if (st == NULL) {
  176. return;
  177. }
  178. if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
  179. struct mt_spm_cond_tables * const tlb = &cond_syspll;
  180. spm_rc_condition_modifier(st->id, st->act, st->value,
  181. MT_RM_CONSTRAINT_ID_SYSPLL, tlb);
  182. } else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
  183. (st->type == CONSTRAINT_RESIDNECY)) {
  184. spm_rc_constraint_status_set(st->id, st->type, st->act,
  185. MT_RM_CONSTRAINT_ID_SYSPLL,
  186. (struct constraint_status * const)st->value,
  187. (struct constraint_status * const)&status);
  188. } else {
  189. INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
  190. }
  191. }
  192. int spm_update_rc_syspll(int state_id, int type, const void *val)
  193. {
  194. int res = MT_RM_STATUS_OK;
  195. switch (type) {
  196. case PLAT_RC_UPDATE_CONDITION:
  197. res = update_rc_condition(state_id, val);
  198. break;
  199. case PLAT_RC_CLKBUF_STATUS:
  200. update_rc_clkbuf_status(val);
  201. break;
  202. case PLAT_RC_UFS_STATUS:
  203. update_rc_ufs_status(val);
  204. break;
  205. case PLAT_RC_IS_USB_PERI:
  206. update_rc_usb_peri(val);
  207. break;
  208. case PLAT_RC_IS_USB_INFRA:
  209. update_rc_usb_infra(val);
  210. break;
  211. case PLAT_RC_STATUS:
  212. update_rc_status(val);
  213. break;
  214. default:
  215. INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
  216. break;
  217. }
  218. return res;
  219. }
  220. unsigned int spm_allow_rc_syspll(int state_id)
  221. {
  222. return CONSTRAINT_SYSPLL_ALLOW;
  223. }
  224. int spm_run_rc_syspll(unsigned int cpu, int state_id)
  225. {
  226. unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
  227. unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
  228. ext_status_syspll = status.is_valid;
  229. if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
  230. #ifdef MT_SPM_USING_SRCLKEN_RC
  231. ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
  232. #else
  233. allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
  234. #endif
  235. }
  236. #ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
  237. mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
  238. MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
  239. #else
  240. (void)allows;
  241. #endif
  242. if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
  243. ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
  244. }
  245. if (IS_PLAT_SUSPEND_ID(state_id)) {
  246. mt_spm_suspend_enter(state_id,
  247. (syspll_ext_opand2 | MT_SPM_EX_OP_CLR_26M_RECORD |
  248. MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT |
  249. MT_SPM_EX_OP_SET_SUSPEND_MODE),
  250. CONSTRAINT_SYSPLL_RESOURCE_REQ);
  251. } else {
  252. mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
  253. }
  254. return 0;
  255. }
  256. int spm_reset_rc_syspll(unsigned int cpu, int state_id)
  257. {
  258. unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
  259. unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
  260. if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
  261. #ifdef MT_SPM_USING_SRCLKEN_RC
  262. ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
  263. #else
  264. allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
  265. #endif
  266. }
  267. #ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
  268. mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
  269. #else
  270. (void)allows;
  271. #endif
  272. if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
  273. ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
  274. }
  275. if (IS_PLAT_SUSPEND_ID(state_id)) {
  276. mt_spm_suspend_resume(state_id,
  277. (syspll_ext_opand2 | MT_SPM_EX_OP_SET_SUSPEND_MODE |
  278. MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
  279. NULL);
  280. } else {
  281. struct wake_status *waken = NULL;
  282. if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
  283. ext_op |= MT_SPM_EX_OP_TRACE_LP;
  284. }
  285. mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
  286. status.enter_cnt++;
  287. if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
  288. status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
  289. }
  290. }
  291. return 0;
  292. }
  293. int spm_get_status_rc_syspll(unsigned int type, void *priv)
  294. {
  295. int ret = MT_RM_STATUS_OK;
  296. if (type == PLAT_RC_STATUS) {
  297. int res = 0;
  298. struct rc_common_state *st = (struct rc_common_state *)priv;
  299. if (st == NULL) {
  300. return MT_RM_STATUS_BAD;
  301. }
  302. res = spm_rc_constraint_status_get(st->id, st->type, st->act,
  303. MT_RM_CONSTRAINT_ID_SYSPLL,
  304. (struct constraint_status * const)&status,
  305. (struct constraint_status * const)st->value);
  306. if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
  307. ret = MT_RM_STATUS_STOP;
  308. }
  309. }
  310. return ret;
  311. }