pncd_private.h 2.8 KB

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  1. /*
  2. * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  3. * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-3-Clause
  6. */
  7. #ifndef __PNCD_PRIVATE_H__
  8. #define __PNCD_PRIVATE_H__
  9. #ifndef __ASSEMBLER__
  10. #include <stdint.h>
  11. #endif /* __ASSEMBLER __ */
  12. #include <context.h>
  13. #ifndef __ASSEMBLER__
  14. #include <lib/cassert.h>
  15. #endif /* __ASSEMBLER __ */
  16. #include <platform_def.h>
  17. /*******************************************************************************
  18. * Constants that allow assembler code to preserve callee-saved registers of the
  19. * C runtime context while performing a security state switch.
  20. ******************************************************************************/
  21. #define PNCD_C_RT_CTX_X19 U(0x0)
  22. #define PNCD_C_RT_CTX_X20 U(0x8)
  23. #define PNCD_C_RT_CTX_X21 U(0x10)
  24. #define PNCD_C_RT_CTX_X22 U(0x18)
  25. #define PNCD_C_RT_CTX_X23 U(0x20)
  26. #define PNCD_C_RT_CTX_X24 U(0x28)
  27. #define PNCD_C_RT_CTX_X25 U(0x30)
  28. #define PNCD_C_RT_CTX_X26 U(0x38)
  29. #define PNCD_C_RT_CTX_X27 U(0x40)
  30. #define PNCD_C_RT_CTX_X28 U(0x48)
  31. #define PNCD_C_RT_CTX_X29 U(0x50)
  32. #define PNCD_C_RT_CTX_X30 U(0x58)
  33. #define PNCD_C_RT_CTX_SIZE U(0x60)
  34. #define PNCD_C_RT_CTX_ENTRIES (PNCD_C_RT_CTX_SIZE >> DWORD_SHIFT)
  35. #ifndef __ASSEMBLER__
  36. /* AArch64 callee saved general purpose register context structure. */
  37. DEFINE_REG_STRUCT(c_rt_regs, PNCD_C_RT_CTX_ENTRIES);
  38. /*
  39. * Compile time assertion to ensure that both the compiler and linker
  40. * have the same double word aligned view of the size of the C runtime
  41. * register context.
  42. */
  43. CASSERT(sizeof(c_rt_regs_t) == PNCD_C_RT_CTX_SIZE,
  44. assert_spd_c_rt_regs_size_mismatch);
  45. /*******************************************************************************
  46. * Structure which helps the SPD to maintain the per-cpu state of the SP.
  47. * 'mpidr' - mpidr of the CPU running PNC
  48. * 'c_rt_ctx' - stack address to restore C runtime context from after
  49. * returning from a synchronous entry into the SP.
  50. * 'cpu_ctx' - space to maintain SP architectural state
  51. ******************************************************************************/
  52. typedef struct pnc_context {
  53. uint64_t mpidr;
  54. uint64_t c_rt_ctx;
  55. cpu_context_t cpu_ctx;
  56. } pnc_context_t;
  57. /*******************************************************************************
  58. * Function & Data prototypes
  59. ******************************************************************************/
  60. uint64_t pncd_enter_sp(uint64_t *c_rt_ctx);
  61. void __dead2 pncd_exit_sp(uint64_t c_rt_ctx, uint64_t ret);
  62. uint64_t pncd_synchronous_sp_entry(pnc_context_t *pnc_ctx);
  63. void __dead2 pncd_synchronous_sp_exit(pnc_context_t *pnc_ctx, uint64_t ret);
  64. void pncd_init_pnc_ep_state(struct entry_point_info *pnc_ep,
  65. uint64_t pc,
  66. pnc_context_t *pnc_ctx);
  67. #endif /* __ASSEMBLER__ */
  68. #endif /* __PNCD_PRIVATE_H__ */