glossary.rst 4.8 KB

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  1. Glossary
  2. ========
  3. This glossary provides definitions for terms and abbreviations used in the TF-A
  4. documentation.
  5. You can find additional definitions in the `Arm Glossary`_.
  6. .. glossary::
  7. :sorted:
  8. AArch32
  9. 32-bit execution state of the ARMv8 ISA
  10. AArch64
  11. 64-bit execution state of the ARMv8 ISA
  12. AMU
  13. Activity Monitor Unit, a hardware monitoring unit introduced by FEAT_AMUv1
  14. that exposes CPU core runtime metrics as a set of counter registers.
  15. API
  16. Application Programming Interface
  17. AT
  18. Address Translation
  19. BTI
  20. Branch Target Identification. An Armv8.5 extension providing additional
  21. control flow integrity around indirect branches and their targets.
  22. CoT
  23. COT
  24. Chain of Trust
  25. CSS
  26. Compute Sub-System
  27. CVE
  28. Common Vulnerabilities and Exposures. A CVE document is commonly used to
  29. describe a publicly-known security vulnerability.
  30. DICE
  31. Device Identifier Composition Engine
  32. DCE
  33. DRTM Configuration Environment
  34. D-CRTM
  35. Dynamic Code Root of Trust for Measurement
  36. DLME
  37. Dynamically Launched Measured Environment
  38. DRTM
  39. Dynamic Root of Trust for Measurement
  40. DPE
  41. DICE Protection Environment
  42. DS-5
  43. Arm Development Studio 5
  44. DSU
  45. DynamIQ Shared Unit
  46. DT
  47. Device Tree
  48. DTB
  49. Device Tree Blob
  50. EL
  51. Exception Level
  52. EHF
  53. Exception Handling Framework
  54. ERRATA_ABI
  55. Errata management firmware interface
  56. FCONF
  57. Firmware Configuration Framework
  58. FDT
  59. Flattened Device Tree
  60. FF-A
  61. Firmware Framework for Arm A-profile
  62. FIP
  63. Firmware Image Package
  64. FVP
  65. Fixed Virtual Platform
  66. FWU
  67. FirmWare Update
  68. GIC
  69. Generic Interrupt Controller
  70. HES
  71. Arm CCA Hardware Enforced Security
  72. ISA
  73. Instruction Set Architecture
  74. Linaro
  75. A collaborative engineering organization consolidating
  76. and optimizing open source software and tools for the Arm architecture.
  77. LSP
  78. A logical secure partition managed by SPM
  79. MMU
  80. Memory Management Unit
  81. MPAM
  82. Memory Partitioning And Monitoring. An optional Armv8.4 extension.
  83. MPMM
  84. Maximum Power Mitigation Mechanism, an optional power management mechanism
  85. supported by some Arm Armv9-A cores.
  86. MPIDR
  87. Multiprocessor Affinity Register
  88. MTE
  89. Memory Tagging Extension. An optional Armv8.5 extension that enables
  90. hardware-assisted memory tagging.
  91. OEN
  92. Owning Entity Number
  93. OP-TEE
  94. Open Portable Trusted Execution Environment. An example of a :term:`TEE`
  95. OTE
  96. Open-source Trusted Execution Environment
  97. PCR
  98. Platform Configuration Register
  99. PDD
  100. Platform Design Document
  101. PAUTH
  102. Pointer Authentication. An optional extension introduced in Armv8.3.
  103. PMF
  104. Performance Measurement Framework
  105. PSA
  106. Platform Security Architecture
  107. PSR
  108. Platform Security Requirements
  109. PSCI
  110. Power State Coordination Interface
  111. RAS
  112. Reliability, Availability, and Serviceability extensions. A mandatory
  113. extension for the Armv8.2 architecture and later. An optional extension to
  114. the base Armv8 architecture.
  115. ROT
  116. Root of Trust
  117. RSE
  118. Runtime Security Engine
  119. SCMI
  120. System Control and Management Interface
  121. SCP
  122. System Control Processor
  123. SDEI
  124. Software Delegated Exception Interface
  125. SDS
  126. Shared Data Storage
  127. SEA
  128. Synchronous External Abort
  129. SiP
  130. SIP
  131. Silicon Provider
  132. SMC
  133. Secure Monitor Call
  134. SMCCC
  135. :term:`SMC` Calling Convention
  136. SoC
  137. System on Chip
  138. SP
  139. Secure Partition
  140. SPD
  141. Secure Payload Dispatcher
  142. SPM
  143. Secure Partition Manager
  144. SRTM
  145. Static Root of Trust for Measurement
  146. SSBS
  147. Speculative Store Bypass Safe. Introduced in Armv8.5, this configuration
  148. bit can be set by software to allow or prevent the hardware from
  149. performing speculative operations.
  150. SVE
  151. Scalable Vector Extension
  152. TBB
  153. Trusted Board Boot
  154. TBBR
  155. Trusted Board Boot Requirements
  156. TCB
  157. Trusted Compute Base
  158. TCG
  159. Trusted Computing Group
  160. TEE
  161. Trusted Execution Environment
  162. TF-A
  163. Trusted Firmware-A
  164. TF-M
  165. Trusted Firmware-M
  166. TLB
  167. Translation Lookaside Buffer
  168. TLK
  169. Trusted Little Kernel. A Trusted OS from NVIDIA.
  170. TPM
  171. Trusted Platform Module
  172. TRNG
  173. True Random Number Generator (hardware based)
  174. TSP
  175. Test Secure Payload
  176. TZC
  177. TrustZone Controller
  178. UBSAN
  179. Undefined Behavior Sanitizer
  180. UEFI
  181. Unified Extensible Firmware Interface
  182. WDOG
  183. Watchdog
  184. XLAT
  185. Translation (abbr.). For example, "XLAT table".
  186. .. _`Arm Glossary`: https://developer.arm.com/support/arm-glossary