threat_model.rst 83 KB

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  1. Generic Threat Model
  2. ********************
  3. ************
  4. Introduction
  5. ************
  6. This document provides a generic threat model for TF-A firmware.
  7. .. _Target of Evaluation:
  8. ********************
  9. Target of Evaluation
  10. ********************
  11. In this threat model, the target of evaluation is the Trusted
  12. Firmware for A-class Processors (TF-A). This includes the boot ROM (BL1),
  13. the trusted boot firmware (BL2) and the runtime EL3 firmware (BL31) as
  14. shown on Figure 1. Everything else on Figure 1 is outside of the scope of
  15. the evaluation.
  16. TF-A can be configured in various ways. In this threat model we consider
  17. only the most basic configuration. To that end we make the following
  18. assumptions:
  19. - All TF-A images are run from either ROM or on-chip trusted SRAM. This means
  20. TF-A is not vulnerable to an attacker that can probe or tamper with off-chip
  21. memory.
  22. - Trusted boot is enabled. This means an attacker can't boot arbitrary images
  23. that are not approved by platform providers.
  24. - There is no Secure-EL2. We don't consider threats that may come with
  25. Secure-EL2 software.
  26. - There are no Root and Realm worlds. These are introduced by :ref:`Realm
  27. Management Extension (RME)`.
  28. The :ref:`Threat Model for TF-A with Arm CCA support` covers these types of
  29. configurations.
  30. - No experimental features are enabled. We do not consider threats that may come
  31. from them.
  32. - The platform's hardware complies with the `PSR specification`_, defining the
  33. bare-minimum security prerequisites for System-on-Chips (SoC).
  34. Data Flow Diagram
  35. =================
  36. Figure 1 shows a high-level data flow diagram for TF-A. The diagram
  37. shows a model of the different components of a TF-A-based system and
  38. their interactions with TF-A. A description of each diagram element
  39. is given on Table 1. On the diagram, the red broken lines indicate
  40. trust boundaries. Components outside of the broken lines
  41. are considered untrusted by TF-A.
  42. .. uml:: ../../resources/diagrams/plantuml/tfa_dfd.puml
  43. :caption: Figure 1: TF-A Data Flow Diagram
  44. .. table:: Table 1: TF-A Data Flow Diagram Description
  45. +-----------------+--------------------------------------------------------+
  46. | Diagram Element | Description |
  47. +=================+========================================================+
  48. | DF1 | | At boot time, images are loaded from non-volatile |
  49. | | memory and verified by TF-A boot firmware. These |
  50. | | images include TF-A BL2 and BL31 images, as well as |
  51. | | other secure and non-secure images. |
  52. +-----------------+--------------------------------------------------------+
  53. | DF2 | | TF-A log system framework outputs debug or |
  54. | | informative messages over a UART interface. |
  55. | | |
  56. | | | Also, characters can be read from a UART interface. |
  57. +-----------------+--------------------------------------------------------+
  58. | DF3 | | Debug and trace IP on a platform can allow access |
  59. | | to registers and memory of TF-A. |
  60. +-----------------+--------------------------------------------------------+
  61. | DF4 | | Secure world software (e.g. trusted OS) interact |
  62. | | with TF-A through SMC call interface and/or shared |
  63. | | memory. |
  64. +-----------------+--------------------------------------------------------+
  65. | DF5 | | Non-secure world software (e.g. rich OS) interact |
  66. | | with TF-A through SMC call interface and/or shared |
  67. | | memory. |
  68. +-----------------+--------------------------------------------------------+
  69. | DF6 | | This path represents the interaction between TF-A and|
  70. | | various hardware IPs such as TrustZone controller |
  71. | | and GIC. At boot time TF-A configures/initializes the|
  72. | | IPs and interacts with them at runtime through |
  73. | | interrupts and registers. |
  74. +-----------------+--------------------------------------------------------+
  75. .. _threat_analysis:
  76. ***************
  77. Threat Analysis
  78. ***************
  79. In this section we identify and provide assessment of potential threats to TF-A
  80. firmware. The threats are identified for each diagram element on the
  81. data flow diagram above.
  82. For each threat, we identify the *asset* that is under threat, the
  83. *threat agent* and the *threat type*. Each threat is given a *risk rating*
  84. that represents the impact and likelihood of that threat. We also discuss
  85. potential mitigations.
  86. Assets
  87. ======
  88. We have identified the following assets for TF-A:
  89. .. table:: Table 2: TF-A Assets
  90. +--------------------+---------------------------------------------------+
  91. | Asset | Description |
  92. +====================+===================================================+
  93. | Sensitive Data | | These include sensitive data that an attacker |
  94. | | must not be able to tamper with (e.g. the Root |
  95. | | of Trust Public Key) or see (e.g. secure logs, |
  96. | | debugging information such as crash reports). |
  97. +--------------------+---------------------------------------------------+
  98. | Code Execution | | This represents the requirement that the |
  99. | | platform should run only TF-A code approved by |
  100. | | the platform provider. |
  101. +--------------------+---------------------------------------------------+
  102. | Availability | | This represents the requirement that TF-A |
  103. | | services should always be available for use. |
  104. +--------------------+---------------------------------------------------+
  105. Threat Agents
  106. =============
  107. To understand the attack surface, it is important to identify potential
  108. attackers, i.e. attack entry points. The following threat agents are
  109. in scope of this threat model.
  110. .. table:: Table 3: Threat Agents
  111. +-------------------+-------------------------------------------------------+
  112. | Threat Agent | Description |
  113. +===================+=======================================================+
  114. | NSCode | | Malicious or faulty code running in the Non-secure |
  115. | | world, including NS-EL0 NS-EL1 and NS-EL2 levels |
  116. +-------------------+-------------------------------------------------------+
  117. | SecCode | | Malicious or faulty code running in the secure |
  118. | | world, including S-EL0 and S-EL1 levels |
  119. +-------------------+-------------------------------------------------------+
  120. | AppDebug | | Physical attacker using debug signals to access |
  121. | | TF-A resources |
  122. +-------------------+-------------------------------------------------------+
  123. | PhysicalAccess | | Physical attacker having access to external device |
  124. | | communication bus and to external flash |
  125. | | communication bus using common hardware |
  126. +-------------------+-------------------------------------------------------+
  127. .. note::
  128. In this threat model an advanced physical attacker that has the capability
  129. to tamper with a hardware (e.g. "rewiring" a chip using a focused
  130. ion beam (FIB) workstation or decapsulate the chip using chemicals) is
  131. considered out-of-scope.
  132. Certain non-invasive physical attacks that do not need modifications to the
  133. chip, notably those like Power Analysis Attacks, are out-of-scope. Power
  134. analysis side-channel attacks represent a category of security threats that
  135. capitalize on information leakage through a device's power consumption during
  136. its normal operation. These attacks leverage the correlation between a
  137. device's power usage and its internal data processing activities. This
  138. correlation provides attackers with the means to extract sensitive
  139. information, including cryptographic keys.
  140. Threat Types
  141. ============
  142. In this threat model we categorize threats using the `STRIDE threat
  143. analysis technique`_. In this technique a threat is categorized as one
  144. or more of these types: ``Spoofing``, ``Tampering``, ``Repudiation``,
  145. ``Information disclosure``, ``Denial of service`` or
  146. ``Elevation of privilege``.
  147. Threat Risk Ratings
  148. ===================
  149. For each threat identified, a risk rating that ranges
  150. from *informational* to *critical* is given based on the likelihood of the
  151. threat occurring if a mitigation is not in place, and the impact of the
  152. threat (i.e. how severe the consequences could be). Table 4 explains each
  153. rating in terms of score, impact and likelihood.
  154. .. table:: Table 4: Rating and score as applied to impact and likelihood
  155. +-----------------------+-------------------------+---------------------------+
  156. | **Rating (Score)** | **Impact** | **Likelihood** |
  157. +=======================+=========================+===========================+
  158. | Critical (5) | | Extreme impact to | | Threat is almost |
  159. | | entire organization | certain to be exploited.|
  160. | | if exploited. | |
  161. | | | | Knowledge of the threat |
  162. | | | and how to exploit it |
  163. | | | are in the public |
  164. | | | domain. |
  165. +-----------------------+-------------------------+---------------------------+
  166. | High (4) | | Major impact to entire| | Threat is relatively |
  167. | | organization or single| easy to detect and |
  168. | | line of business if | exploit by an attacker |
  169. | | exploited | with little skill. |
  170. +-----------------------+-------------------------+---------------------------+
  171. | Medium (3) | | Noticeable impact to | | A knowledgeable insider |
  172. | | line of business if | or expert attacker could|
  173. | | exploited. | exploit the threat |
  174. | | | without much difficulty.|
  175. +-----------------------+-------------------------+---------------------------+
  176. | Low (2) | | Minor damage if | | Exploiting the threat |
  177. | | exploited or could | would require |
  178. | | be used in conjunction| considerable expertise |
  179. | | with other | and resources |
  180. | | vulnerabilities to | |
  181. | | perform a more serious| |
  182. | | attack | |
  183. +-----------------------+-------------------------+---------------------------+
  184. | Informational (1) | | Poor programming | | Threat is not likely |
  185. | | practice or poor | to be exploited on its |
  186. | | design decision that | own, but may be used to |
  187. | | may not represent an | gain information for |
  188. | | immediate risk on its | launching another |
  189. | | own, but may have | attack |
  190. | | security implications | |
  191. | | if multiplied and/or | |
  192. | | combined with other | |
  193. | | threats. | |
  194. +-----------------------+-------------------------+---------------------------+
  195. Aggregate risk scores are assigned to identified threats;
  196. specifically, the impact score multiplied by the likelihood score.
  197. For example, a threat with high likelihood and low impact would have an
  198. aggregate risk score of eight (8); that is, four (4) for high likelihood
  199. multiplied by two (2) for low impact. The aggregate risk score determines
  200. the finding's overall risk level, as shown in the following table.
  201. .. table:: Table 5: Overall risk levels and corresponding aggregate scores
  202. +---------------------+-----------------------------------+
  203. | Overall Risk Level | Aggregate Risk Score |
  204. | | (Impact multiplied by Likelihood) |
  205. +=====================+===================================+
  206. | Critical | 20–25 |
  207. +---------------------+-----------------------------------+
  208. | High | 12–19 |
  209. +---------------------+-----------------------------------+
  210. | Medium | 6–11 |
  211. +---------------------+-----------------------------------+
  212. | Low | 2–5 |
  213. +---------------------+-----------------------------------+
  214. | Informational | 1 |
  215. +---------------------+-----------------------------------+
  216. The likelihood and impact of a threat depends on the
  217. target environment in which TF-A is running. For example, attacks
  218. that require physical access are unlikely in server environments while
  219. they are more common in Internet of Things(IoT) environments.
  220. In this threat model we consider three target environments:
  221. ``Internet of Things(IoT)``, ``Mobile`` and ``Server``.
  222. Threat Assessment
  223. =================
  224. The following threats were identified by applying STRIDE analysis on
  225. each diagram element of the data flow diagram.
  226. For each threat, we strive to indicate whether the mitigations are currently
  227. implemented or not. However, the answer to this question is not always straight
  228. forward. Some mitigations are partially implemented in the generic code but also
  229. rely on the platform code to implement some bits of it. This threat model aims
  230. to be platform-independent and it is important to keep in mind that such threats
  231. only get mitigated if the platform code properly fulfills its responsibilities.
  232. Also, some mitigations require enabling specific features, which must be
  233. explicitly turned on via a build flag.
  234. When such conditions must be met, these are highlighted in the ``Mitigations
  235. implemented?`` box.
  236. As our :ref:`Target of Evaluation` is made of several, distinct firmware images,
  237. some threats are confined in specific images, while others apply to each of
  238. them. To help developers implement mitigations in the right place, threats below
  239. are categorized based on the firmware image that should mitigate them.
  240. .. _General Threats:
  241. General Threats for All Firmware Images
  242. ---------------------------------------
  243. +------------------------+---------------------------------------------------+
  244. | ID | 05 |
  245. +========================+===================================================+
  246. | Threat | | **Information leak via UART logs** |
  247. | | |
  248. | | | During the development stages of software it is |
  249. | | common to print all sorts of information on the |
  250. | | console, including sensitive or confidential |
  251. | | information such as crash reports with detailed |
  252. | | information of the CPU state, current registers |
  253. | | values, privilege level or stack dumps. |
  254. | | |
  255. | | | This information is useful when debugging |
  256. | | problems before releasing the production |
  257. | | version but it could be used by an attacker |
  258. | | to develop a working exploit if left enabled in |
  259. | | the production version. |
  260. | | |
  261. | | | This happens when directly logging sensitive |
  262. | | information and more subtly when logging |
  263. | | side-channel information that can be used by an |
  264. | | attacker to learn about sensitive information. |
  265. +------------------------+---------------------------------------------------+
  266. | Diagram Elements | DF2 |
  267. +------------------------+---------------------------------------------------+
  268. | Affected TF-A | BL1, BL2, BL31 |
  269. | Components | |
  270. +------------------------+---------------------------------------------------+
  271. | Assets | Sensitive Data |
  272. +------------------------+---------------------------------------------------+
  273. | Threat Agent | AppDebug |
  274. +------------------------+---------------------------------------------------+
  275. | Threat Type | Information Disclosure |
  276. +------------------------+------------------+----------------+---------------+
  277. | Application | Server | IoT | Mobile |
  278. +------------------------+------------------+----------------+---------------+
  279. | Impact | N/A | Low (2) | Low (2) |
  280. +------------------------+------------------+----------------+---------------+
  281. | Likelihood | N/A | High (4) | High (4) |
  282. +------------------------+------------------+----------------+---------------+
  283. | Total Risk Rating | N/A | Medium (8) | Medium (8) |
  284. +------------------------+------------------+----------------+---------------+
  285. | Mitigations | | Remove sensitive information logging in |
  286. | | production releases. |
  287. | | |
  288. | | | Do not conditionally log information depending |
  289. | | on potentially sensitive data. |
  290. | | |
  291. | | | Do not log high precision timing information. |
  292. +------------------------+---------------------------------------------------+
  293. | Mitigations | | Yes / Platform Specific. |
  294. | implemented? | Requires the right build options to be used. |
  295. | | |
  296. | | | Crash reporting is only enabled for debug |
  297. | | builds by default, see ``CRASH_REPORTING`` |
  298. | | build option. |
  299. | | |
  300. | | | The log level can be tuned at build time, from |
  301. | | very verbose to no output at all. See |
  302. | | ``LOG_LEVEL`` build option. By default, release |
  303. | | builds are a lot less verbose than debug ones |
  304. | | but still produce some output. |
  305. | | |
  306. | | | Messages produced by the platform code should |
  307. | | use the appropriate level of verbosity so as |
  308. | | not to leak sensitive information in production |
  309. | | builds. |
  310. +------------------------+---------------------------------------------------+
  311. +------------------------+----------------------------------------------------+
  312. | ID | 06 |
  313. +========================+====================================================+
  314. | Threat | | **An attacker can read sensitive data and |
  315. | | execute arbitrary code through the external |
  316. | | debug and trace interface** |
  317. | | |
  318. | | | Arm processors include hardware-assisted debug |
  319. | | and trace features that can be controlled without|
  320. | | the need for software operating on the platform. |
  321. | | If left enabled without authentication, this |
  322. | | feature can be used by an attacker to inspect and|
  323. | | modify TF-A registers and memory allowing the |
  324. | | attacker to read sensitive data and execute |
  325. | | arbitrary code. |
  326. +------------------------+----------------------------------------------------+
  327. | Diagram Elements | DF3 |
  328. +------------------------+----------------------------------------------------+
  329. | Affected TF-A | BL1, BL2, BL31 |
  330. | Components | |
  331. +------------------------+----------------------------------------------------+
  332. | Assets | Code Execution, Sensitive Data |
  333. +------------------------+----------------------------------------------------+
  334. | Threat Agent | AppDebug |
  335. +------------------------+----------------------------------------------------+
  336. | Threat Type | Tampering, Information Disclosure, |
  337. | | Elevation of privilege |
  338. +------------------------+------------------+---------------+-----------------+
  339. | Application | Server | IoT | Mobile |
  340. +------------------------+------------------+---------------+-----------------+
  341. | Impact | N/A | High (4) | High (4) |
  342. +------------------------+------------------+---------------+-----------------+
  343. | Likelihood | N/A | Critical (5) | Critical (5) |
  344. +------------------------+------------------+---------------+-----------------+
  345. | Total Risk Rating | N/A | Critical (20) | Critical (20) |
  346. +------------------------+------------------+---------------+-----------------+
  347. | Mitigations | Disable the debug and trace capability for |
  348. | | production releases or enable proper debug |
  349. | | authentication as recommended by [`DEN0034`_]. |
  350. +------------------------+----------------------------------------------------+
  351. | Mitigations | | Platform specific. |
  352. | implemented? | |
  353. | | | Configuration of debug and trace capabilities is |
  354. | | entirely platform specific. |
  355. +------------------------+----------------------------------------------------+
  356. +------------------------+------------------------------------------------------+
  357. | ID | 08 |
  358. +========================+======================================================+
  359. | Threat | | **Memory corruption due to memory overflows and |
  360. | | lack of boundary checking when accessing resources |
  361. | | could allow an attacker to execute arbitrary code, |
  362. | | modify some state variable to change the normal |
  363. | | flow of the program, or leak sensitive |
  364. | | information** |
  365. | | |
  366. | | | Like in other software, TF-A has multiple points |
  367. | | where memory corruption security errors can arise. |
  368. | | |
  369. | | | Some of the errors include integer overflow, |
  370. | | buffer overflow, incorrect array boundary checks, |
  371. | | and incorrect error management. |
  372. | | Improper use of asserts instead of proper input |
  373. | | validations might also result in these kinds of |
  374. | | errors in release builds. |
  375. +------------------------+------------------------------------------------------+
  376. | Diagram Elements | DF4, DF5 |
  377. +------------------------+------------------------------------------------------+
  378. | Affected TF-A | BL1, BL2, BL31 |
  379. | Components | |
  380. +------------------------+------------------------------------------------------+
  381. | Assets | Code Execution, Sensitive Data |
  382. +------------------------+------------------------------------------------------+
  383. | Threat Agent | NSCode, SecCode |
  384. +------------------------+------------------------------------------------------+
  385. | Threat Type | Tampering, Information Disclosure, |
  386. | | Elevation of Privilege |
  387. +------------------------+-------------------+-----------------+----------------+
  388. | Application | Server | IoT | Mobile |
  389. +------------------------+-------------------+-----------------+----------------+
  390. | Impact | Critical (5) | Critical (5) | Critical (5) |
  391. +------------------------+-------------------+-----------------+----------------+
  392. | Likelihood | Medium (3 | Medium (3) | Medium (3) |
  393. +------------------------+-------------------+-----------------+----------------+
  394. | Total Risk Rating | High (15) | High (15) | High (15) |
  395. +------------------------+-------------------+-----------------+----------------+
  396. | Mitigations | | 1) Use proper input validation. |
  397. | | |
  398. | | | 2) Code reviews, testing. |
  399. +------------------------+------------------------------------------------------+
  400. | Mitigations | | 1) Yes. |
  401. | implemented? | Data received from normal world, such as addresses |
  402. | | and sizes identifying memory regions, are |
  403. | | sanitized before being used. These security checks |
  404. | | make sure that the normal world software does not |
  405. | | access memory beyond its limit. |
  406. | | |
  407. | | | By default *asserts* are only used to check for |
  408. | | programming errors in debug builds. Other types of |
  409. | | errors are handled through condition checks that |
  410. | | remain enabled in release builds. See |
  411. | | `TF-A error handling policy`_. TF-A provides an |
  412. | | option to use *asserts* in release builds, however |
  413. | | we recommend using proper runtime checks instead |
  414. | | of relying on asserts in release builds. |
  415. | | |
  416. | | | 2) Yes. |
  417. | | TF-A uses a combination of manual code reviews |
  418. | | and automated program analysis and testing to |
  419. | | detect and fix memory corruption bugs. All TF-A |
  420. | | code including platform code go through manual |
  421. | | code reviews. Additionally, static code analysis |
  422. | | is performed using Coverity Scan on all TF-A code. |
  423. | | The code is also tested with |
  424. | | `Trusted Firmware-A Tests`_ on Juno and FVP |
  425. | | platforms. |
  426. +------------------------+------------------------------------------------------+
  427. +------------------------+----------------------------------------------------+
  428. | ID | 11 |
  429. +========================+====================================================+
  430. | Threat | | **Misconfiguration of the Memory Management Unit |
  431. | | (MMU) may allow a normal world software to |
  432. | | access sensitive data, execute arbitrary |
  433. | | code or access otherwise restricted HW |
  434. | | interface** |
  435. | | |
  436. | | | A misconfiguration of the MMU could |
  437. | | lead to an open door for software running in the |
  438. | | normal world to access sensitive data or even |
  439. | | execute code if the proper security mechanisms |
  440. | | are not in place. |
  441. +------------------------+----------------------------------------------------+
  442. | Diagram Elements | DF5, DF6 |
  443. +------------------------+----------------------------------------------------+
  444. | Affected TF-A | BL1, BL2, BL31 |
  445. | Components | |
  446. +------------------------+----------------------------------------------------+
  447. | Assets | Sensitive Data, Code execution |
  448. +------------------------+----------------------------------------------------+
  449. | Threat Agent | NSCode |
  450. +------------------------+----------------------------------------------------+
  451. | Threat Type | Information Disclosure, Elevation of Privilege |
  452. +------------------------+-----------------+-----------------+----------------+
  453. | Application | Server | IoT | Mobile |
  454. +------------------------+-----------------+-----------------+----------------+
  455. | Impact | Critical (5) | Critical (5) | Critical (5) |
  456. +------------------------+-----------------+-----------------+----------------+
  457. | Likelihood | High (4) | High (4) | High (4) |
  458. +------------------------+-----------------+-----------------+----------------+
  459. | Total Risk Rating | Critical (20) | Critical (20) | Critical (20) |
  460. +------------------------+-----------------+-----------------+----------------+
  461. | Mitigations | When configuring access permissions, the |
  462. | | principle of least privilege ought to be |
  463. | | enforced. This means we should not grant more |
  464. | | privileges than strictly needed, e.g. code |
  465. | | should be read-only executable, read-only data |
  466. | | should be read-only execute-never, and so on. |
  467. +------------------------+----------------------------------------------------+
  468. | Mitigations | | Platform specific. |
  469. | implemented? | |
  470. | | | MMU configuration is platform specific, |
  471. | | therefore platforms need to make sure that the |
  472. | | correct attributes are assigned to memory |
  473. | | regions. |
  474. | | |
  475. | | | TF-A provides a library which abstracts the |
  476. | | low-level details of MMU configuration. It |
  477. | | provides well-defined and tested APIs. |
  478. | | Platforms are encouraged to use it to limit the |
  479. | | risk of misconfiguration. |
  480. +------------------------+----------------------------------------------------+
  481. +------------------------+-----------------------------------------------------+
  482. | ID | 13 |
  483. +========================+=====================================================+
  484. | Threat | | **Leaving sensitive information in the memory, |
  485. | | can allow an attacker to retrieve them.** |
  486. | | |
  487. | | | Accidentally leaving not-needed sensitive data in |
  488. | | internal buffers can leak them if an attacker |
  489. | | gains access to memory due to a vulnerability. |
  490. +------------------------+-----------------------------------------------------+
  491. | Diagram Elements | DF4, DF5 |
  492. +------------------------+-----------------------------------------------------+
  493. | Affected TF-A | BL1, BL2, BL31 |
  494. | Components | |
  495. +------------------------+-----------------------------------------------------+
  496. | Assets | Sensitive Data |
  497. +------------------------+-----------------------------------------------------+
  498. | Threat Agent | NSCode, SecCode |
  499. +------------------------+-----------------------------------------------------+
  500. | Threat Type | Information Disclosure |
  501. +------------------------+-------------------+----------------+----------------+
  502. | Application | Server | IoT | Mobile |
  503. +------------------------+-------------------+----------------+----------------+
  504. | Impact | Critical (5) | Critical (5) | Critical (5) |
  505. +------------------------+-------------------+----------------+----------------+
  506. | Likelihood | Medium (3) | Medium (3) | Medium (3) |
  507. +------------------------+-------------------+----------------+----------------+
  508. | Total Risk Rating | High (15) | High (15) | High (15) |
  509. +------------------------+-------------------+----------------+----------------+
  510. | Mitigations | Clear the sensitive data from internal buffers as |
  511. | | soon as they are not needed anymore. |
  512. +------------------------+-----------------------------------------------------+
  513. | Mitigations | | Yes / Platform specific |
  514. | implemented? | |
  515. +------------------------+-----------------------------------------------------+
  516. +------------------------+-----------------------------------------------------+
  517. | ID | 15 |
  518. +========================+=====================================================+
  519. | Threat | | **Improper handling of input data received over |
  520. | | a UART interface may allow an attacker to tamper |
  521. | | with TF-A execution environment.** |
  522. | | |
  523. | | | The consequences of the attack depend on the |
  524. | | the exact usage of input data received over UART. |
  525. | | Examples are injection of arbitrary data, |
  526. | | sensitive data tampering, influencing the |
  527. | | execution path, denial of service (if using |
  528. | | blocking I/O). This list may not be exhaustive. |
  529. +------------------------+-----------------------------------------------------+
  530. | Diagram Elements | DF2, DF4, DF5 |
  531. +------------------------+-----------------------------------------------------+
  532. | Affected TF-A | BL1, BL2, BL31 |
  533. | Components | |
  534. +------------------------+-----------------------------------------------------+
  535. | Assets | Sensitive Data, Code Execution, Availability |
  536. +------------------------+-----------------------------------------------------+
  537. | Threat Agent | NSCode, SecCode |
  538. +------------------------+-----------------------------------------------------+
  539. | Threat Type | Tampering, Information Disclosure, Denial of |
  540. | | service, Elevation of privilege. |
  541. +------------------------+-------------------+----------------+----------------+
  542. | Application | Server | IoT | Mobile |
  543. +------------------------+-------------------+----------------+----------------+
  544. | Impact | Critical (5) | Critical (5) | Critical (5) |
  545. +------------------------+-------------------+----------------+----------------+
  546. | Likelihood | Critical (5) | Critical (5) | Critical (5) |
  547. +------------------------+-------------------+----------------+----------------+
  548. | Total Risk Rating | Critical (25) | Critical (25) | Critical (25) |
  549. +------------------------+-------------------+----------------+----------------+
  550. | Mitigations | | By default, the code to read input data from UART |
  551. | | interfaces is disabled (see `ENABLE_CONSOLE_GETC` |
  552. | | build option). It should only be enabled on a |
  553. | | need basis. |
  554. | | |
  555. | | | Data received over UART interfaces should be |
  556. | | treated as untrusted data. As such, it should be |
  557. | | properly sanitized and handled with caution. |
  558. +------------------------+-----------------------------------------------------+
  559. | Mitigations | | Platform specific. |
  560. | implemented? | |
  561. | | | Generic code does not read any input data from |
  562. | | UART interface(s). |
  563. +------------------------+-----------------------------------------------------+
  564. +------------------------+-----------------------------------------------------+
  565. | ID | 16 |
  566. +========================+=====================================================+
  567. | Threat | | **An attacker could analyse the timing behaviour |
  568. | | of implemented methods in the system to infer |
  569. | | sensitive information.** |
  570. | | |
  571. | | | A timing side-channel attack is a type of attack |
  572. | | that exploits variations in the time it takes a |
  573. | | system to perform different operations. This |
  574. | | form of attack focuses on analyzing the time- |
  575. | | related information leakage that occurs during |
  576. | | the execution of cryptographic algorithms or |
  577. | | other security-sensitive processes. By observing |
  578. | | these timing differences, an attacker can gain |
  579. | | insights into the internal workings of a system |
  580. | | and potentially extract sensitive information. |
  581. | | Sensitive information that, when revealed even |
  582. | | partially, could heighten the susceptibility to |
  583. | | traditional attacks like brute-force attacks. |
  584. +------------------------+-----------------------------------------------------+
  585. | Diagram Elements | DF2 |
  586. +------------------------+-----------------------------------------------------+
  587. | Affected TF-A | BL1, BL2, BL31 |
  588. | Components | |
  589. +------------------------+-----------------------------------------------------+
  590. | Assets | Sensitive Data |
  591. +------------------------+-----------------------------------------------------+
  592. | Threat Agent | AppDebug |
  593. +------------------------+-----------------------------------------------------+
  594. | Threat Type | Information Disclosure |
  595. +------------------------+------------------+----------------+-----------------+
  596. | Application | Server | IoT | Mobile |
  597. +------------------------+------------------+----------------+-----------------+
  598. | Impact | Critical (5) | Critical (5) | Critical (5) |
  599. +------------------------+------------------+----------------+-----------------+
  600. | Likelihood | Critical (5) | Critical (5) | Critical (5) |
  601. +------------------------+------------------+----------------+-----------------+
  602. | Total Risk Rating | Critical (25) | Critical (25) | Critical (25) |
  603. +------------------------+------------------+----------------+-----------------+
  604. | Mitigations | | Ensure that the execution time of critical |
  605. | | operations is constant and independent of |
  606. | | secret data. This prevents attackers from |
  607. | | exploiting timing differences to infer |
  608. | | information about sensitive data. |
  609. | | |
  610. | | | Introduce random delays/timing jitter or dummy |
  611. | | operations to make the timing behavior of program|
  612. | | execution less predictable. This can disrupt the |
  613. | | correlation between the execution time and |
  614. | | sensitive data. |
  615. | | |
  616. +------------------------+-----------------------------------------------------+
  617. | Mitigations | | Not implemented |
  618. | implemented? | |
  619. +------------------------+-----------------------------------------------------+
  620. .. _Boot Firmware Threats:
  621. Threats to be Mitigated by the Boot Firmware
  622. --------------------------------------------
  623. The boot firmware here refers to the boot ROM (BL1) and the trusted boot
  624. firmware (BL2). Typically it does not stay resident in memory and it is
  625. dismissed once execution has reached the runtime EL3 firmware (BL31). Thus, past
  626. that point in time, the threats below can no longer be exploited.
  627. Note, however, that this is not necessarily true on all platforms. Platform
  628. vendors should review these threats to make sure they cannot be exploited
  629. nonetheless once execution has reached the runtime EL3 firmware.
  630. +------------------------+----------------------------------------------------+
  631. | ID | 01 |
  632. +========================+====================================================+
  633. | Threat | | **An attacker can mangle firmware images to |
  634. | | execute arbitrary code** |
  635. | | |
  636. | | | Some TF-A images are loaded from external |
  637. | | storage. It is possible for an attacker to access|
  638. | | the external flash memory and change its contents|
  639. | | physically, through the Rich OS, or using the |
  640. | | updating mechanism to modify the non-volatile |
  641. | | images to execute arbitrary code. |
  642. +------------------------+----------------------------------------------------+
  643. | Diagram Elements | DF1, DF4, DF5 |
  644. +------------------------+----------------------------------------------------+
  645. | Affected TF-A | BL2, BL31 |
  646. | Components | |
  647. +------------------------+----------------------------------------------------+
  648. | Assets | Code Execution |
  649. +------------------------+----------------------------------------------------+
  650. | Threat Agent | PhysicalAccess, NSCode, SecCode |
  651. +------------------------+----------------------------------------------------+
  652. | Threat Type | Tampering, Elevation of Privilege |
  653. +------------------------+------------------+-----------------+---------------+
  654. | Application | Server | IoT | Mobile |
  655. +------------------------+------------------+-----------------+---------------+
  656. | Impact | Critical (5) | Critical (5) | Critical (5) |
  657. +------------------------+------------------+-----------------+---------------+
  658. | Likelihood | Critical (5) | Critical (5) | Critical (5) |
  659. +------------------------+------------------+-----------------+---------------+
  660. | Total Risk Rating | Critical (25) | Critical (25) | Critical (25) |
  661. +------------------------+------------------+-----------------+---------------+
  662. | Mitigations | | 1) Implement the `Trusted Board Boot (TBB)`_ |
  663. | | feature which prevents malicious firmware from |
  664. | | running on the platform by authenticating all |
  665. | | firmware images. |
  666. | | |
  667. | | | 2) Perform extra checks on unauthenticated data, |
  668. | | such as FIP metadata, prior to use. |
  669. +------------------------+----------------------------------------------------+
  670. | Mitigations | | 1) Yes, provided that the ``TRUSTED_BOARD_BOOT`` |
  671. | implemented? | build option is set to 1. |
  672. | | |
  673. | | | 2) Yes. |
  674. +------------------------+----------------------------------------------------+
  675. +------------------------+----------------------------------------------------+
  676. | ID | 02 |
  677. +========================+====================================================+
  678. | Threat | | **An attacker may attempt to boot outdated, |
  679. | | potentially vulnerable firmware image** |
  680. | | |
  681. | | | When updating firmware, an attacker may attempt |
  682. | | to rollback to an older version that has unfixed |
  683. | | vulnerabilities. |
  684. +------------------------+----------------------------------------------------+
  685. | Diagram Elements | DF1, DF4, DF5 |
  686. +------------------------+----------------------------------------------------+
  687. | Affected TF-A | BL2, BL31 |
  688. | Components | |
  689. +------------------------+----------------------------------------------------+
  690. | Assets | Code Execution |
  691. +------------------------+----------------------------------------------------+
  692. | Threat Agent | PhysicalAccess, NSCode, SecCode |
  693. +------------------------+----------------------------------------------------+
  694. | Threat Type | Tampering |
  695. +------------------------+------------------+-----------------+---------------+
  696. | Application | Server | IoT | Mobile |
  697. +------------------------+------------------+-----------------+---------------+
  698. | Impact | Critical (5) | Critical (5) | Critical (5) |
  699. +------------------------+------------------+-----------------+---------------+
  700. | Likelihood | Critical (5) | Critical (5) | Critical (5) |
  701. +------------------------+------------------+-----------------+---------------+
  702. | Total Risk Rating | Critical (25) | Critical (25) | Critical (25) |
  703. +------------------------+------------------+-----------------+---------------+
  704. | Mitigations | Implement anti-rollback protection using |
  705. | | non-volatile counters (NV counters) as required |
  706. | | by `TBBR-Client specification`_. |
  707. +------------------------+----------------------------------------------------+
  708. | Mitigations | | Yes / Platform specific. |
  709. | implemented? | |
  710. | | | After a firmware image is validated, the image |
  711. | | revision number taken from a certificate |
  712. | | extension field is compared with the |
  713. | | corresponding NV counter stored in hardware to |
  714. | | make sure the new counter value is larger than |
  715. | | the current counter value. |
  716. | | |
  717. | | | **Platforms must implement this protection using |
  718. | | platform specific hardware NV counters.** |
  719. +------------------------+----------------------------------------------------+
  720. +------------------------+-------------------------------------------------------+
  721. | ID | 03 |
  722. +========================+=======================================================+
  723. | Threat | | **An attacker can use Time-of-Check-Time-of-Use |
  724. | | (TOCTOU) attack to bypass image authentication |
  725. | | during the boot process** |
  726. | | |
  727. | | | Time-of-Check-Time-of-Use (TOCTOU) threats occur |
  728. | | when the security check is produced before the time |
  729. | | the resource is accessed. If an attacker is sitting |
  730. | | in the middle of the off-chip images, they could |
  731. | | change the binary containing executable code right |
  732. | | after the integrity and authentication check has |
  733. | | been performed. |
  734. +------------------------+-------------------------------------------------------+
  735. | Diagram Elements | DF1 |
  736. +------------------------+-------------------------------------------------------+
  737. | Affected TF-A | BL1, BL2 |
  738. | Components | |
  739. +------------------------+-------------------------------------------------------+
  740. | Assets | Code Execution, Sensitive Data |
  741. +------------------------+-------------------------------------------------------+
  742. | Threat Agent | PhysicalAccess |
  743. +------------------------+-------------------------------------------------------+
  744. | Threat Type | Elevation of Privilege |
  745. +------------------------+---------------------+-----------------+---------------+
  746. | Application | Server | IoT | Mobile |
  747. +------------------------+---------------------+-----------------+---------------+
  748. | Impact | N/A | Critical (5) | Critical (5) |
  749. +------------------------+---------------------+-----------------+---------------+
  750. | Likelihood | N/A | Medium (3) | Medium (3) |
  751. +------------------------+---------------------+-----------------+---------------+
  752. | Total Risk Rating | N/A | High (15) | High (15) |
  753. +------------------------+---------------------+-----------------+---------------+
  754. | Mitigations | Copy image to on-chip memory before authenticating |
  755. | | it. |
  756. +------------------------+-------------------------------------------------------+
  757. | Mitigations | | Platform specific. |
  758. | implemented? | |
  759. | | | The list of images to load and their location is |
  760. | | platform specific. Platforms are responsible for |
  761. | | arranging images to be loaded in on-chip memory. |
  762. +------------------------+-------------------------------------------------------+
  763. +------------------------+-------------------------------------------------------+
  764. | ID | 04 |
  765. +========================+=======================================================+
  766. | Threat | | **An attacker with physical access can execute |
  767. | | arbitrary image by bypassing the signature |
  768. | | verification stage using glitching techniques** |
  769. | | |
  770. | | | Glitching (Fault injection) attacks attempt to put |
  771. | | a hardware into a undefined state by manipulating an|
  772. | | environmental variable such as power supply. |
  773. | | |
  774. | | | TF-A relies on a chain of trust that starts with the|
  775. | | ROTPK, which is the key stored inside the chip and |
  776. | | the root of all validation processes. If an attacker|
  777. | | can break this chain of trust, they could execute |
  778. | | arbitrary code on the device. This could be |
  779. | | achieved with physical access to the device by |
  780. | | attacking the normal execution flow of the |
  781. | | process using glitching techniques that target |
  782. | | points where the image is validated against the |
  783. | | signature. |
  784. +------------------------+-------------------------------------------------------+
  785. | Diagram Elements | DF1 |
  786. +------------------------+-------------------------------------------------------+
  787. | Affected TF-A | BL1, BL2 |
  788. | Components | |
  789. +------------------------+-------------------------------------------------------+
  790. | Assets | Code Execution |
  791. +------------------------+-------------------------------------------------------+
  792. | Threat Agent | PhysicalAccess |
  793. +------------------------+-------------------------------------------------------+
  794. | Threat Type | Tampering, Elevation of Privilege |
  795. +------------------------+---------------------+-----------------+---------------+
  796. | Application | Server | IoT | Mobile |
  797. +------------------------+---------------------+-----------------+---------------+
  798. | Impact | N/A | Critical (5) | Critical (5) |
  799. +------------------------+---------------------+-----------------+---------------+
  800. | Likelihood | N/A | Medium (3) | Medium (3) |
  801. +------------------------+---------------------+-----------------+---------------+
  802. | Total Risk Rating | N/A | High (15) | High (15) |
  803. +------------------------+---------------------+-----------------+---------------+
  804. | Mitigations | Mechanisms to detect clock glitch and power |
  805. | | variations. |
  806. +------------------------+-------------------------------------------------------+
  807. | Mitigations | | No. |
  808. | implemented? | |
  809. | | | The most effective mitigation is adding glitching |
  810. | | detection and mitigation circuit at the hardware |
  811. | | level. |
  812. | | |
  813. | | | However, software techniques, such as adding |
  814. | | redundant checks when performing conditional |
  815. | | branches that are security sensitive, can be used |
  816. | | to harden TF-A against such attacks. |
  817. | | **At the moment TF-A doesn't implement such |
  818. | | mitigations.** |
  819. +------------------------+-------------------------------------------------------+
  820. .. topic:: Measured Boot Threats (or lack of)
  821. In the current Measured Boot design the following components form the |TCB|:
  822. - BL1, BL2, BL31
  823. - Secure world components
  824. - RMM (if RME extension is implemented)
  825. - The configuration data of the above components
  826. Across various Measured Boot backends, the data recorded during the flow as
  827. well as the criticality of this data can vary. In most cases, these attributes
  828. are considered valuable assets and are protected against potential attacks:
  829. - Image measurement: the digest value of a component produced by a hash
  830. function.
  831. - Signer-id: the digest value of the image verification publiy key. The
  832. verification public key is part of the image metadata.
  833. In addition to these, other metadata attributes (image version, hash algorithm
  834. identifier, etc) could be recorded during the Measured Boot process. But these
  835. are not critical data.
  836. In this context, an attack means modifying the measurement data (image or
  837. public key hash) or recording arbitrary data as valid measurements.
  838. The current Measured Boot design consists of two main parts. A frontend, which
  839. is responsible for taking the measurements, and a backend which is responsible
  840. for storing them. |TF-A| makes it possible to integrate various backends. Some
  841. of these are implemented by the |TF-A| projects, while others are part of
  842. different projects, and |TF-A| provides an integration layer.
  843. - TCG-compliant Event Log: Implemented by |TF-A|. Measurements are stored in
  844. the Event Log which is located on the secure on-chip memory of the AP. The
  845. address of the Event Log buffer is handed off between boot stages and new
  846. measurements are appended to the Event Log. A limitation of the current
  847. Measured Boot implementation in |TF-A| is that it does not extend the
  848. measurements into a |PCR| of a Discrete |TPM|, where measurements would
  849. be securely stored and protected against tampering.
  850. - `CCA Measured Boot`_: Implemented by |TF-M|. Measurements are stored in
  851. |HES| secure on-chip memory. |HES| implements protection against tampering
  852. its on-chip memory. |HES| interface is available for BL1 and BL2.
  853. - `DICE Protection Environment`_ (DPE): Implemented by |TF-M|. Measurements
  854. are stored in |RSE| secure on-chip memory. |RSE| implements protection
  855. against tampering its on-chip memory. DPE provides additional protection
  856. against unauthorized access by malicious actors through the use of one-time
  857. context handles and the identification of the client's target locality
  858. (location of the client).
  859. Beyond the measurements (image digest and signer-id) there are no other assets
  860. to protect or threats to defend against that could compromise |TF-A| execution
  861. environment's security.
  862. There are general security assets and threats associated with remote/delegated
  863. attestation. However, these are outside the |TF-A| security boundary and
  864. should be dealt with by the appropriate agent in the platform/system.
  865. Since current Measured Boot design does not use local attestation, there would
  866. be no further assets to protect (like unsealed keys).
  867. System integrators must carefully evaluate the security requirement and
  868. capabilities of their platform and choose an appropriate Measured Boot
  869. solution.
  870. .. _Runtime Firmware Threats:
  871. Threats to be Mitigated by the Runtime EL3 Firmware
  872. ---------------------------------------------------
  873. +------------------------+------------------------------------------------------+
  874. | ID | 07 |
  875. +========================+======================================================+
  876. | Threat | | **An attacker can perform a denial-of-service |
  877. | | attack by using a broken SMC call that causes the |
  878. | | system to reboot or enter into unknown state.** |
  879. | | |
  880. | | | Secure and non-secure clients access TF-A services |
  881. | | through SMC calls. Malicious code can attempt to |
  882. | | place the TF-A runtime into an inconsistent state |
  883. | | by calling unimplemented SMC call or by passing |
  884. | | invalid arguments. |
  885. +------------------------+------------------------------------------------------+
  886. | Diagram Elements | DF4, DF5 |
  887. +------------------------+------------------------------------------------------+
  888. | Affected TF-A | BL31 |
  889. | Components | |
  890. +------------------------+------------------------------------------------------+
  891. | Assets | Availability |
  892. +------------------------+------------------------------------------------------+
  893. | Threat Agent | NSCode, SecCode |
  894. +------------------------+------------------------------------------------------+
  895. | Threat Type | Denial of Service |
  896. +------------------------+-------------------+----------------+-----------------+
  897. | Application | Server | IoT | Mobile |
  898. +------------------------+-------------------+----------------+-----------------+
  899. | Impact | Medium (3) | Medium (3) | Medium (3) |
  900. +------------------------+-------------------+----------------+-----------------+
  901. | Likelihood | High (4) | High (4) | High (4) |
  902. +------------------------+-------------------+----------------+-----------------+
  903. | Total Risk Rating | High (12) | High (12) | High (12) |
  904. +------------------------+-------------------+----------------+-----------------+
  905. | Mitigations | Validate SMC function ids and arguments before using |
  906. | | them. |
  907. +------------------------+------------------------------------------------------+
  908. | Mitigations | | Yes / Platform specific. |
  909. | implemented? | |
  910. | | | For standard services, all input is validated. |
  911. | | |
  912. | | | Platforms that implement SiP services must also |
  913. | | validate SMC call arguments. |
  914. +------------------------+------------------------------------------------------+
  915. +------------------------+------------------------------------------------------+
  916. | ID | 09 |
  917. +========================+======================================================+
  918. | Threat | | **Improperly handled SMC calls can leak register |
  919. | | contents** |
  920. | | |
  921. | | | When switching between worlds, TF-A register state |
  922. | | can leak to software in different security |
  923. | | contexts. |
  924. +------------------------+------------------------------------------------------+
  925. | Diagram Elements | DF4, DF5 |
  926. +------------------------+------------------------------------------------------+
  927. | Affected TF-A | BL31 |
  928. | Components | |
  929. +------------------------+------------------------------------------------------+
  930. | Assets | Sensitive Data |
  931. +------------------------+------------------------------------------------------+
  932. | Threat Agent | NSCode, SecCode |
  933. +------------------------+------------------------------------------------------+
  934. | Threat Type | Information Disclosure |
  935. +------------------------+-------------------+----------------+-----------------+
  936. | Application | Server | IoT | Mobile |
  937. +------------------------+-------------------+----------------+-----------------+
  938. | Impact | Medium (3) | Medium (3) | Medium (3) |
  939. +------------------------+-------------------+----------------+-----------------+
  940. | Likelihood | High (4) | High (4) | High (4) |
  941. +------------------------+-------------------+----------------+-----------------+
  942. | Total Risk Rating | High (12) | High (12) | High (12) |
  943. +------------------------+-------------------+----------------+-----------------+
  944. | Mitigations | Save and restore registers when switching contexts. |
  945. +------------------------+------------------------------------------------------+
  946. | Mitigations | | Yes. |
  947. | implemented? | |
  948. | | | This is the default behaviour in TF-A. |
  949. | | Build options are also provided to save/restore |
  950. | | additional registers such as floating-point |
  951. | | registers. These should be enabled if required. |
  952. +------------------------+------------------------------------------------------+
  953. +------------------------+-----------------------------------------------------+
  954. | ID | 10 |
  955. +========================+=====================================================+
  956. | Threat | | **SMC calls can leak sensitive information from |
  957. | | TF-A memory via microarchitectural side channels**|
  958. | | |
  959. | | | Microarchitectural side-channel attacks such as |
  960. | | `Spectre`_ can be used to leak data across |
  961. | | security boundaries. An attacker might attempt to |
  962. | | use this kind of attack to leak sensitive |
  963. | | data from TF-A memory. |
  964. +------------------------+-----------------------------------------------------+
  965. | Diagram Elements | DF4, DF5 |
  966. +------------------------+-----------------------------------------------------+
  967. | Affected TF-A | BL31 |
  968. | Components | |
  969. +------------------------+-----------------------------------------------------+
  970. | Assets | Sensitive Data |
  971. +------------------------+-----------------------------------------------------+
  972. | Threat Agent | SecCode, NSCode |
  973. +------------------------+-----------------------------------------------------+
  974. | Threat Type | Information Disclosure |
  975. +------------------------+-------------------+----------------+----------------+
  976. | Application | Server | IoT | Mobile |
  977. +------------------------+-------------------+----------------+----------------+
  978. | Impact | Medium (3) | Medium (3) | Medium (3) |
  979. +------------------------+-------------------+----------------+----------------+
  980. | Likelihood | Medium (3) | Medium (3) | Medium (3) |
  981. +------------------------+-------------------+----------------+----------------+
  982. | Total Risk Rating | Medium (9) | Medium (9) | Medium (9) |
  983. +------------------------+-------------------+----------------+----------------+
  984. | Mitigations | Enable appropriate side-channel protections. |
  985. +------------------------+-----------------------------------------------------+
  986. | Mitigations | | Yes / Platform specific. |
  987. | implemented? | |
  988. | | | TF-A implements software mitigations for Spectre |
  989. | | type attacks as recommended by `Cache Speculation |
  990. | | Side-channels`_ for the generic code. |
  991. | | |
  992. | | | SiPs should implement similar mitigations for |
  993. | | code that is deemed to be vulnerable to such |
  994. | | attacks. |
  995. +------------------------+-----------------------------------------------------+
  996. +------------------------+-----------------------------------------------------+
  997. | ID | 12 |
  998. +========================+=====================================================+
  999. | Threat | | **Incorrect configuration of Performance Monitor |
  1000. | | Unit (PMU) counters can allow an attacker to |
  1001. | | mount side-channel attacks using information |
  1002. | | exposed by the counters** |
  1003. | | |
  1004. | | | Non-secure software can configure PMU registers |
  1005. | | to count events at any exception level and in |
  1006. | | both Secure and Non-secure states. This allows |
  1007. | | a Non-secure software (or a lower-level Secure |
  1008. | | software) to potentially carry out |
  1009. | | side-channel timing attacks against TF-A. |
  1010. +------------------------+-----------------------------------------------------+
  1011. | Diagram Elements | DF5, DF6 |
  1012. +------------------------+-----------------------------------------------------+
  1013. | Affected TF-A | BL31 |
  1014. | Components | |
  1015. +------------------------+-----------------------------------------------------+
  1016. | Assets | Sensitive Data |
  1017. +------------------------+-----------------------------------------------------+
  1018. | Threat Agent | NSCode |
  1019. +------------------------+-----------------------------------------------------+
  1020. | Threat Type | Information Disclosure |
  1021. +------------------------+-------------------+----------------+----------------+
  1022. | Application | Server | IoT | Mobile |
  1023. +------------------------+-------------------+----------------+----------------+
  1024. | Impact | Medium (3) | Medium (3) | Medium (3) |
  1025. +------------------------+-------------------+----------------+----------------+
  1026. | Likelihood | Low (2) | Low (2) | Low (2) |
  1027. +------------------------+-------------------+----------------+----------------+
  1028. | Total Risk Rating | Medium (6) | Medium (6) | Medium (6) |
  1029. +------------------------+-------------------+----------------+----------------+
  1030. | Mitigations | Follow mitigation strategies as described in |
  1031. | | `Secure Development Guidelines`_. |
  1032. +------------------------+-----------------------------------------------------+
  1033. | Mitigations | | Yes / platform specific. |
  1034. | implemented? | |
  1035. | | | General events and cycle counting in the Secure |
  1036. | | world is prohibited by default when applicable. |
  1037. | | |
  1038. | | | However, on some implementations (e.g. PMUv3) |
  1039. | | Secure world event counting depends on external |
  1040. | | debug interface signals, i.e. Secure world event |
  1041. | | counting is enabled if external debug is enabled. |
  1042. | | |
  1043. | | | Configuration of debug signals is platform |
  1044. | | specific, therefore platforms need to make sure |
  1045. | | that external debug is disabled in production or |
  1046. | | proper debug authentication is in place. This |
  1047. | | should be the case if threat #06 is properly |
  1048. | | mitigated. |
  1049. +------------------------+-----------------------------------------------------+
  1050. Threats to be Mitigated by an External Agent Outside of TF-A
  1051. ------------------------------------------------------------
  1052. +------------------------+-----------------------------------------------------+
  1053. | ID | 14 |
  1054. +========================+=====================================================+
  1055. | Threat | | **Attacker wants to execute an arbitrary or |
  1056. | | untrusted binary as the secure OS.** |
  1057. | | |
  1058. | | | When the option OPTEE_ALLOW_SMC_LOAD is enabled, |
  1059. | | this trusts the non-secure world up until the |
  1060. | | point it issues the SMC call to load the Secure |
  1061. | | BL32 payload. If a compromise occurs before the |
  1062. | | SMC call is invoked, then arbitrary code execution|
  1063. | | in S-EL1 can occur or arbitrary memory in EL3 can |
  1064. | | be overwritten. |
  1065. +------------------------+-----------------------------------------------------+
  1066. | Diagram Elements | DF5 |
  1067. +------------------------+-----------------------------------------------------+
  1068. | Affected TF-A | BL31, BL32 |
  1069. | Components | |
  1070. +------------------------+-----------------------------------------------------+
  1071. | Assets | Code Execution, Sensitive Data |
  1072. +------------------------+-----------------------------------------------------+
  1073. | Threat Agent | NSCode |
  1074. +------------------------+-----------------------------------------------------+
  1075. | Threat Type | Tampering, Information Disclosure, |
  1076. | | Elevation of privilege |
  1077. +------------------------+-----------------+-----------------+-----------------+
  1078. | Application | Server | IoT | Mobile |
  1079. +------------------------+-----------------+-----------------+-----------------+
  1080. | Impact | Critical (5) | Critical (5) | Critical (5) |
  1081. +------------------------+-----------------+-----------------+-----------------+
  1082. | Likelihood | High (4) | High (4) | High (4) |
  1083. +------------------------+-----------------+-----------------+-----------------+
  1084. | Total Risk Rating | Critical (20) | Critical (20) | Critical (20) |
  1085. +------------------------+-----------------+-----------------+-----------------+
  1086. | Mitigations | When enabling the option OPTEE_ALLOW_SMC_LOAD, |
  1087. | | the non-secure OS must be considered a closed |
  1088. | | platform up until the point the SMC can be invoked |
  1089. | | to load OP-TEE. |
  1090. +------------------------+-----------------------------------------------------+
  1091. | Mitigations | | None in TF-A itself. This option is only used by |
  1092. | implemented? | ChromeOS currently which has other mechanisms to |
  1093. | | to mitigate this threat which are described in |
  1094. | | `OP-TEE Dispatcher`_. |
  1095. +------------------------+-----------------------------------------------------+
  1096. --------------
  1097. *Copyright (c) 2021-2024, Arm Limited. All rights reserved.*
  1098. .. _STRIDE threat analysis technique: https://docs.microsoft.com/en-us/azure/security/develop/threat-modeling-tool-threats#stride-model
  1099. .. _DEN0034: https://developer.arm.com/documentation/den0034/latest
  1100. .. _Cache Speculation Side-channels: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
  1101. .. _Spectre: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
  1102. .. _TBBR-Client specification: https://developer.arm.com/documentation/den0006/d/
  1103. .. _Trusted Board Boot (TBB): https://trustedfirmware-a.readthedocs.io/en/latest/design/trusted-board-boot.html
  1104. .. _TF-A error handling policy: https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#error-handling-and-robustness
  1105. .. _Secure Development Guidelines: https://trustedfirmware-a.readthedocs.io/en/latest/process/security-hardening.html#secure-development-guidelines
  1106. .. _Trusted Firmware-A Tests: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/about/
  1107. .. _OP-TEE Dispatcher: https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/components/spd/optee-dispatcher.rst
  1108. .. _PSR Specification: https://developer.arm.com/documentation/den0106/0100
  1109. .. _CCA Measured Boot: https://trustedfirmware-m.readthedocs.io/projects/tf-m-extras/en/latest/partitions/measured_boot_integration_guide.html
  1110. .. _DICE Protection Environment: https://trustedfirmware-m.readthedocs.io/projects/tf-m-extras/en/latest/partitions/dice_protection_environment/dice_protection_environment.html