fvp_r_bl1_main.c 6.9 KB

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  1. /*
  2. * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <assert.h>
  7. #include "../../../../bl1/bl1_private.h"
  8. #include <arch.h>
  9. #include <arch_features.h>
  10. #include <arch_helpers.h>
  11. #include <bl1/bl1.h>
  12. #include <common/bl_common.h>
  13. #include <common/build_message.h>
  14. #include <common/debug.h>
  15. #include <drivers/auth/auth_mod.h>
  16. #include <drivers/console.h>
  17. #include <lib/cpus/errata.h>
  18. #include <lib/utils.h>
  19. #include <smccc_helpers.h>
  20. #include <tools_share/uuid.h>
  21. #include <plat/arm/common/plat_arm.h>
  22. #include <plat/common/platform.h>
  23. #include <platform_def.h>
  24. void cm_prepare_el2_exit(void);
  25. void bl1_run_next_image(const struct entry_point_info *bl_ep_info);
  26. /*******************************************************************************
  27. * Function to perform late architectural and platform specific initialization.
  28. * It also queries the platform to load and run next BL image. Only called
  29. * by the primary cpu after a cold boot.
  30. ******************************************************************************/
  31. void bl1_transfer_bl33(void)
  32. {
  33. unsigned int image_id;
  34. /* Get the image id of next image to load and run. */
  35. image_id = bl1_plat_get_next_image_id();
  36. #if !ARM_DISABLE_TRUSTED_WDOG
  37. /* Disable watchdog before leaving BL1 */
  38. plat_arm_secure_wdt_stop();
  39. #endif
  40. bl1_run_next_image(&bl1_plat_get_image_desc(image_id)->ep_info);
  41. }
  42. /*******************************************************************************
  43. * This function locates and loads the BL33 raw binary image in the trusted SRAM.
  44. * Called by the primary cpu after a cold boot.
  45. * TODO: Add support for alternative image load mechanism e.g using virtio/elf
  46. * loader etc.
  47. ******************************************************************************/
  48. void bl1_load_bl33(void)
  49. {
  50. image_desc_t *desc;
  51. image_info_t *info;
  52. int err;
  53. /* Get the image descriptor */
  54. desc = bl1_plat_get_image_desc(BL33_IMAGE_ID);
  55. assert(desc != NULL);
  56. /* Get the image info */
  57. info = &desc->image_info;
  58. INFO("BL1: Loading BL33\n");
  59. err = bl1_plat_handle_pre_image_load(BL33_IMAGE_ID);
  60. if (err != 0) {
  61. ERROR("Failure in pre image load handling of BL33 (%d)\n", err);
  62. plat_error_handler(err);
  63. }
  64. err = load_auth_image(BL33_IMAGE_ID, info);
  65. if (err != 0) {
  66. ERROR("Failed to load BL33 firmware.\n");
  67. plat_error_handler(err);
  68. }
  69. /* Allow platform to handle image information. */
  70. err = bl1_plat_handle_post_image_load(BL33_IMAGE_ID);
  71. if (err != 0) {
  72. ERROR("Failure in post image load handling of BL33 (%d)\n", err);
  73. plat_error_handler(err);
  74. }
  75. NOTICE("BL1: Booting BL33\n");
  76. }
  77. /*******************************************************************************
  78. * This function prepares for entry to BL33
  79. ******************************************************************************/
  80. void bl1_prepare_next_image(unsigned int image_id)
  81. {
  82. unsigned int mode = MODE_EL1;
  83. image_desc_t *desc;
  84. entry_point_info_t *next_bl_ep;
  85. #if CTX_INCLUDE_AARCH32_REGS
  86. /*
  87. * Ensure that the build flag to save AArch32 system registers in CPU
  88. * context is not set for AArch64-only platforms.
  89. */
  90. if (el_implemented(1) == EL_IMPL_A64ONLY) {
  91. ERROR("EL1 supports AArch64-only. Please set build flag %s",
  92. "CTX_INCLUDE_AARCH32_REGS = 0\n");
  93. panic();
  94. }
  95. #endif
  96. /* Get the image descriptor. */
  97. desc = bl1_plat_get_image_desc(image_id);
  98. assert(desc != NULL);
  99. /* Get the entry point info. */
  100. next_bl_ep = &desc->ep_info;
  101. /* FVP-R is only secure */
  102. assert(GET_SECURITY_STATE(next_bl_ep->h.attr) == SECURE);
  103. /* Prepare the SPSR for the next BL image. */
  104. next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode,
  105. (uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
  106. /* Allow platform to make change */
  107. bl1_plat_set_ep_info(image_id, next_bl_ep);
  108. /* Prepare context for the next EL */
  109. cm_prepare_el2_exit();
  110. /* Indicate that image is in execution state. */
  111. desc->state = IMAGE_STATE_EXECUTED;
  112. print_entry_point_info(next_bl_ep);
  113. }
  114. /*******************************************************************************
  115. * Setup function for BL1.
  116. ******************************************************************************/
  117. void bl1_setup(void)
  118. {
  119. /* Perform early platform-specific setup */
  120. bl1_early_platform_setup();
  121. /* Perform late platform-specific setup */
  122. bl1_plat_arch_setup();
  123. }
  124. /*******************************************************************************
  125. * Function to perform late architectural and platform specific initialization.
  126. * It also queries the platform to load and run next BL image. Only called
  127. * by the primary cpu after a cold boot.
  128. ******************************************************************************/
  129. void bl1_main(void)
  130. {
  131. unsigned int image_id;
  132. /* Announce our arrival */
  133. NOTICE(FIRMWARE_WELCOME_STR);
  134. NOTICE("BL1: %s\n", build_version_string);
  135. NOTICE("BL1: %s\n", build_message);
  136. INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
  137. print_errata_status();
  138. #if ENABLE_ASSERTIONS
  139. u_register_t val;
  140. /*
  141. * Ensure that MMU/Caches and coherency are turned on
  142. */
  143. val = read_sctlr_el2();
  144. assert((val & SCTLR_M_BIT) != 0U);
  145. assert((val & SCTLR_C_BIT) != 0U);
  146. assert((val & SCTLR_I_BIT) != 0U);
  147. /*
  148. * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
  149. * provided platform value
  150. */
  151. val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
  152. /*
  153. * If CWG is zero, then no CWG information is available but we can
  154. * at least check the platform value is less than the architectural
  155. * maximum.
  156. */
  157. if (val != 0) {
  158. assert(SIZE_FROM_LOG2_WORDS(val) == CACHE_WRITEBACK_GRANULE);
  159. } else {
  160. assert(MAX_CACHE_LINE_SIZE >= CACHE_WRITEBACK_GRANULE);
  161. }
  162. #endif /* ENABLE_ASSERTIONS */
  163. /* Perform remaining generic architectural setup from ELmax */
  164. bl1_arch_setup();
  165. #if TRUSTED_BOARD_BOOT
  166. /* Initialize authentication module */
  167. auth_mod_init();
  168. #endif /* TRUSTED_BOARD_BOOT */
  169. /* Perform platform setup in BL1. */
  170. bl1_platform_setup();
  171. /* Get the image id of next image to load and run. */
  172. image_id = bl1_plat_get_next_image_id();
  173. /*
  174. * We currently interpret any image id other than
  175. * BL2_IMAGE_ID as the start of firmware update.
  176. */
  177. if (image_id == BL33_IMAGE_ID) {
  178. bl1_load_bl33();
  179. } else {
  180. NOTICE("BL1-FWU: *******FWU Process Started*******\n");
  181. }
  182. bl1_prepare_next_image(image_id);
  183. console_flush();
  184. bl1_transfer_bl33();
  185. }
  186. /*******************************************************************************
  187. * Function called just before handing over to the next BL to inform the user
  188. * about the boot progress. In debug mode, also print details about the BL
  189. * image's execution context.
  190. ******************************************************************************/
  191. void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
  192. {
  193. NOTICE("BL1: Booting BL31\n");
  194. print_entry_point_info(bl_ep_info);
  195. }
  196. #if SPIN_ON_BL1_EXIT
  197. void print_debug_loop_message(void)
  198. {
  199. NOTICE("BL1: Debug loop, spinning forever\n");
  200. NOTICE("BL1: Please connect the debugger to continue\n");
  201. }
  202. #endif