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arm-trusted-firmware
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plat
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aspeed
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ast2700
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include
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platform_def.h

platform_def.h 1.6 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2023, Aspeed Technology Inc.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef PLATFORM_DEF_H
    8. 

  8. #define PLATFORM_DEF_H
    9. 

  9. 

  10. #include <arch.h>
    11. 

  11. #include <plat/common/common_def.h>
    12. 

  12. #include <platform_reg.h>
    13. 

  13. 

  14. #define PLATFORM_STACK_SIZE		UL(0x1000)
    15. 

  15. 

  16. /* cpu topology */
    17. 

  17. #define PLATFORM_SYSTEM_COUNT		U(1)
    18. 

  18. #define PLATFORM_CLUSTER_COUNT		U(1)
    19. 

  19. #define PLATFORM_CORE_PRIMARY		U(0)
    20. 

  20. #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4)
    21. 

  21. #define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER_COUNT * \
    22. 

  22. 					 PLATFORM_CORE_COUNT_PER_CLUSTER)
    23. 

  23. 

  24. /* power domain */
    25. 

  25. #define PLAT_MAX_PWR_LVL		U(1)
    26. 

  26. #define PLAT_NUM_PWR_DOMAINS		U(5)
    27. 

  27. #define PLAT_MAX_RET_STATE		U(1)
    28. 

  28. #define PLAT_MAX_OFF_STATE		U(2)
    29. 

  29. 

  30. /* cache line size */
    31. 

  31. #define CACHE_WRITEBACK_SHIFT		U(6)
    32. 

  32. #define CACHE_WRITEBACK_GRANULE		(U(1) << CACHE_WRITEBACK_SHIFT)
    33. 

  33. 

  34. /* translation tables */
    35. 

  35. #define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 36)
    36. 

  36. #define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 40)
    37. 

  37. #define MAX_XLAT_TABLES			U(8)
    38. 

  38. #define MAX_MMAP_REGIONS		U(32)
    39. 

  39. 

  40. /* BL31 region */
    41. 

  41. #define BL31_BASE			ULL(0x430000000)
    42. 

  42. #define BL31_SIZE			SZ_512K
    43. 

  43. #define BL31_LIMIT			(BL31_BASE + BL31_SIZE)
    44. 

  44. 

  45. /* BL32 region */
    46. 

  46. #define BL32_BASE			BL31_LIMIT
    47. 

  47. #define BL32_SIZE			SZ_16M
    48. 

  48. #define BL32_LIMIT			(BL32_BASE + BL32_SIZE)
    49. 

  49. 

  50. /* console */
    51. 

  51. #define CONSOLE_UART_BASE		UART12_BASE
    52. 

  52. #define CONSOLE_UART_CLKIN_HZ		U(1846153)
    53. 

  53. #define CONSOLE_UART_BAUDRATE		U(115200)
    54. 

  54. 

  55. /* CLK information */
    56. 

  56. #define CLKIN_25M			UL(25000000)
    57. 

  57. 

  58. #define PLAT_CLK_GATE_NUM		U(29)
    59. 

  59. #define PLAT_CLK_HPLL			(PLAT_CLK_GATE_NUM + 5)
    60. 

  60. #define PLAT_CLK_DPLL			(PLAT_CLK_GATE_NUM + 6)
    61. 

  61. #define PLAT_CLK_MPLL			(PLAT_CLK_GATE_NUM + 7)
    62. 

  62. 

  63. #endif /* PLATFORM_DEF_H */
    64.