hi6220_regs_pin.h 1.2 KB

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  1. /*
  2. * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #ifndef HI6220_REGS_PIN_H
  7. #define HI6220_REGS_PIN_H
  8. #define IOMG_BASE 0xF7010000
  9. #define IOMG_SD_CLK (IOMG_BASE + 0x0C)
  10. #define IOMG_SD_CMD (IOMG_BASE + 0x10)
  11. #define IOMG_SD_DATA0 (IOMG_BASE + 0x14)
  12. #define IOMG_SD_DATA1 (IOMG_BASE + 0x18)
  13. #define IOMG_SD_DATA2 (IOMG_BASE + 0x1C)
  14. #define IOMG_SD_DATA3 (IOMG_BASE + 0x20)
  15. #define IOMG_GPIO24 (IOMG_BASE + 0x140)
  16. #define IOMG_MUX_FUNC0 0
  17. #define IOMG_MUX_FUNC1 1
  18. #define IOMG_MUX_FUNC2 2
  19. #define IOCG1_BASE 0xF7010800
  20. #define IOCG2_BASE 0xF8001800
  21. #define IOCG_SD_CLK (IOCG1_BASE + 0x0C)
  22. #define IOCG_SD_CMD (IOCG1_BASE + 0x10)
  23. #define IOCG_SD_DATA0 (IOCG1_BASE + 0x14)
  24. #define IOCG_SD_DATA1 (IOCG1_BASE + 0x18)
  25. #define IOCG_SD_DATA2 (IOCG1_BASE + 0x1C)
  26. #define IOCG_SD_DATA3 (IOCG1_BASE + 0x20)
  27. #define IOCG_GPIO24 (IOCG1_BASE + 0x150)
  28. #define IOCG_GPIO8 (IOCG2_BASE + 0x30)
  29. #define IOCG_DRIVE_8MA (2 << 4)
  30. #define IOCG_DRIVE_10MA (3 << 4)
  31. #define IOCG_INPUT_16MA 0x64
  32. #define IOCG_INPUT_12MA 0x54
  33. #define IOCG_PULLDOWN (1 << 1)
  34. #define IOCG_PULLUP (1 << 0)
  35. #endif /* HI6220_REGS_PIN_H */