marvell_topology.c 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384
  1. /*
  2. * Copyright (C) 2018 Marvell International Ltd.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. * https://spdx.org/licenses
  6. */
  7. #include <plat_marvell.h>
  8. /* The power domain tree descriptor */
  9. unsigned char marvell_power_domain_tree_desc[PLAT_MARVELL_CLUSTER_COUNT + 1];
  10. /*****************************************************************************
  11. * This function dynamically constructs the topology according to
  12. * PLAT_MARVELL_CLUSTER_COUNT and returns it.
  13. *****************************************************************************
  14. */
  15. const unsigned char *plat_get_power_domain_tree_desc(void)
  16. {
  17. int i;
  18. /*
  19. * The power domain tree does not have a single system level power
  20. * domain i.e. a single root node. The first entry in the power domain
  21. * descriptor specifies the number of power domains at the highest power
  22. * level.
  23. * For Marvell Platform this is the number of cluster power domains.
  24. */
  25. marvell_power_domain_tree_desc[0] = PLAT_MARVELL_CLUSTER_COUNT;
  26. for (i = 0; i < PLAT_MARVELL_CLUSTER_COUNT; i++)
  27. marvell_power_domain_tree_desc[i + 1] =
  28. PLAT_MARVELL_CLUSTER_CORE_COUNT;
  29. return marvell_power_domain_tree_desc;
  30. }
  31. /*****************************************************************************
  32. * This function validates an MPIDR by checking whether it falls within the
  33. * acceptable bounds. An error code (-1) is returned if an incorrect mpidr
  34. * is passed.
  35. *****************************************************************************
  36. */
  37. int marvell_check_mpidr(u_register_t mpidr)
  38. {
  39. unsigned int nb_id, cluster_id, cpu_id;
  40. mpidr &= MPIDR_AFFINITY_MASK;
  41. if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK |
  42. MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT))
  43. return -1;
  44. /* Get north bridge ID */
  45. nb_id = MPIDR_AFFLVL3_VAL(mpidr);
  46. cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
  47. cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
  48. if (nb_id >= PLAT_MARVELL_CLUSTER_COUNT)
  49. return -1;
  50. if (cluster_id >= PLAT_MARVELL_CLUSTER_COUNT)
  51. return -1;
  52. if (cpu_id >= PLAT_MARVELL_CLUSTER_CORE_COUNT)
  53. return -1;
  54. return 0;
  55. }
  56. /*****************************************************************************
  57. * This function implements a part of the critical interface between the PSCI
  58. * generic layer and the platform that allows the former to query the platform
  59. * to convert an MPIDR to a unique linear index. An error code (-1) is returned
  60. * in case the MPIDR is invalid.
  61. *****************************************************************************
  62. */
  63. int plat_core_pos_by_mpidr(u_register_t mpidr)
  64. {
  65. if (marvell_check_mpidr(mpidr) == -1)
  66. return -1;
  67. return plat_marvell_calc_core_pos(mpidr);
  68. }