apusys_security_ctrl_plat.c 2.4 KB

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  1. /*
  2. * Copyright (c) 2024, MediaTek Inc. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #define ENABLE_SMPU_PROTECT (0)
  7. #if ENABLE_SMPU_PROTECT
  8. #include "emi.h"
  9. #include "mt_emi.h"
  10. #endif
  11. #include <common/debug.h>
  12. #include <lib/mmio.h>
  13. #include <apusys_security_ctrl_plat.h>
  14. #define APUSYS_SEC_FW_EMI_REGION (23)
  15. #define bits_clr(x, m, o) (x & (~(m << o)))
  16. #define bits_set(x, v, m, o) ((bits_clr(x, m, o)) | ((v & m) << o))
  17. static void sec_sideband_init(void)
  18. {
  19. uint32_t value = mmio_read_32(SEC_CTRL_SIDE_BAND);
  20. value = bits_set(value, SEC_CTRL_NARE_DOMAIN, SEC_CTRL_DOMAIN_MASK,
  21. SEC_CTRL_NARE_DOMAIN_SHF);
  22. value = bits_set(value, SEC_CTRL_NARE_NS, SEC_CTRL_NS_MASK, SEC_CTRL_NARE_NS_SHF);
  23. value = bits_set(value, SEC_CTRL_SARE0_DOMAIN, SEC_CTRL_DOMAIN_MASK,
  24. SEC_CTRL_SARE0_DOMAIN_SHF);
  25. value = bits_set(value, SEC_CTRL_SARE0_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE0_NS_SHF);
  26. value = bits_set(value, SEC_CTRL_SARE1_DOMAIN, SEC_CTRL_DOMAIN_MASK,
  27. SEC_CTRL_SARE1_DOMAIN_SHF);
  28. value = bits_set(value, SEC_CTRL_SARE1_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE1_NS_SHF);
  29. mmio_write_32(SEC_CTRL_SIDE_BAND, value);
  30. }
  31. static void domain_remap_init(void)
  32. {
  33. const uint32_t remap_domains[] = {
  34. D0_REMAP_DOMAIN, D1_REMAP_DOMAIN, D2_REMAP_DOMAIN, D3_REMAP_DOMAIN,
  35. D4_REMAP_DOMAIN, D5_REMAP_DOMAIN, D6_REMAP_DOMAIN, D7_REMAP_DOMAIN,
  36. D8_REMAP_DOMAIN, D9_REMAP_DOMAIN, D10_REMAP_DOMAIN, D11_REMAP_DOMAIN,
  37. D12_REMAP_DOMAIN, D13_REMAP_DOMAIN, D14_REMAP_DOMAIN, D15_REMAP_DOMAIN,
  38. };
  39. uint32_t lower_domain = 0;
  40. uint32_t higher_domain = 0;
  41. int i;
  42. for (i = 0; i < ARRAY_SIZE(remap_domains); i++) {
  43. if (i < SEC_CTRL_REG_DOMAIN_NUM)
  44. lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS));
  45. else
  46. higher_domain |= (remap_domains[i] <<
  47. ((i - SEC_CTRL_REG_DOMAIN_NUM) * REG_DOMAIN_BITS));
  48. }
  49. mmio_write_32(SEC_CTRL_SOC2APU_SET1_0, lower_domain);
  50. mmio_write_32(SEC_CTRL_SOC2APU_SET1_1, higher_domain);
  51. mmio_setbits_32(APU_SEC_CON, SEC_CTRL_DOMAIN_REMAP_SEL);
  52. }
  53. void apusys_security_ctrl_init(void)
  54. {
  55. domain_remap_init();
  56. sec_sideband_init();
  57. }
  58. int apusys_plat_setup_sec_mem(void)
  59. {
  60. #if ENABLE_SMPU_PROTECT
  61. return sip_emi_mpu_set_protection(APU_RESERVE_MEMORY >> EMI_MPU_ALIGN_BITS,
  62. (APU_RESERVE_MEMORY + APU_RESERVE_SIZE) >> EMI_MPU_ALIGN_BITS,
  63. APUSYS_SEC_FW_EMI_REGION);
  64. #else
  65. INFO("%s: Bypass SMPU protection setup.\n", __func__);
  66. return 0;
  67. #endif
  68. }