common.mk 4.1 KB

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  1. #
  2. # Copyright (c) 2023-2024, Linaro Limited and Contributors. All rights reserved.
  3. #
  4. # SPDX-License-Identifier: BSD-3-Clause
  5. #
  6. include lib/libfdt/libfdt.mk
  7. include common/fdt_wrappers.mk
  8. PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
  9. -I${PLAT_QEMU_COMMON_PATH}/include \
  10. -I${PLAT_QEMU_PATH}/include \
  11. -Iinclude/common/tbbr
  12. ifeq (${ARCH},aarch32)
  13. QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S
  14. else
  15. QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
  16. lib/cpus/aarch64/cortex_a53.S \
  17. lib/cpus/aarch64/cortex_a55.S \
  18. lib/cpus/aarch64/cortex_a57.S \
  19. lib/cpus/aarch64/cortex_a72.S \
  20. lib/cpus/aarch64/cortex_a76.S \
  21. lib/cpus/aarch64/cortex_a710.S \
  22. lib/cpus/aarch64/neoverse_n_common.S \
  23. lib/cpus/aarch64/neoverse_n1.S \
  24. lib/cpus/aarch64/neoverse_v1.S \
  25. lib/cpus/aarch64/neoverse_n2.S \
  26. lib/cpus/aarch64/qemu_max.S
  27. PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
  28. endif
  29. PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
  30. ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
  31. drivers/arm/pl011/${ARCH}/pl011_console.S
  32. include lib/xlat_tables_v2/xlat_tables.mk
  33. PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
  34. ifneq ($(ENABLE_STACK_PROTECTOR), 0)
  35. PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
  36. endif
  37. BL1_SOURCES += drivers/io/io_semihosting.c \
  38. drivers/io/io_storage.c \
  39. drivers/io/io_fip.c \
  40. drivers/io/io_memmap.c \
  41. lib/semihosting/semihosting.c \
  42. lib/semihosting/${ARCH}/semihosting_call.S \
  43. ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
  44. ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
  45. ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \
  46. ${QEMU_CPU_LIBS}
  47. BL2_SOURCES += drivers/io/io_semihosting.c \
  48. drivers/io/io_storage.c \
  49. drivers/io/io_fip.c \
  50. drivers/io/io_memmap.c \
  51. lib/semihosting/semihosting.c \
  52. lib/semihosting/${ARCH}/semihosting_call.S \
  53. ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
  54. ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
  55. ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
  56. ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
  57. ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
  58. common/desc_image_load.c \
  59. common/fdt_fixup.c
  60. BL31_SOURCES += ${QEMU_CPU_LIBS} \
  61. lib/semihosting/semihosting.c \
  62. lib/semihosting/${ARCH}/semihosting_call.S \
  63. plat/common/plat_psci_common.c \
  64. ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
  65. ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
  66. common/fdt_fixup.c \
  67. ${QEMU_GIC_SOURCES}
  68. # CPU flag enablement
  69. ifeq (${ARCH},aarch64)
  70. # Cpu core architecture level:
  71. # v8.0: a53, a57, a72
  72. # v8.2: a55, a76, n1
  73. # v8.4: v1
  74. # v9.0: a710, n2
  75. #
  76. #
  77. # We go v8.0 by default and will enable all features we want
  78. ARM_ARCH_MAJOR ?= 8
  79. ARM_ARCH_MINOR ?= 0
  80. # 8.0
  81. ENABLE_FEAT_CSV2_2 := 2
  82. # 8.1
  83. ENABLE_FEAT_PAN := 2
  84. ENABLE_FEAT_VHE := 2
  85. # 8.2
  86. # TF-A currently does not permit dynamic detection of FEAT_RAS
  87. # so this is the only safe setting
  88. ENABLE_FEAT_RAS := 0
  89. # 8.4
  90. ENABLE_FEAT_SEL2 := 2
  91. ENABLE_FEAT_DIT := 2
  92. ENABLE_TRF_FOR_NS := 2
  93. # 8.5
  94. ENABLE_FEAT_RNG := 2
  95. # TF-A currently does not do dynamic detection of FEAT_SB.
  96. # Compiler puts SB instruction when it is enabled.
  97. ENABLE_FEAT_SB := 0
  98. # 8.6
  99. ENABLE_FEAT_ECV := 2
  100. ENABLE_FEAT_FGT := 2
  101. # 8.7
  102. ENABLE_FEAT_HCX := 2
  103. # SPM_MM is not compatible with ENABLE_SVE_FOR_NS (build breaks)
  104. ifeq (${SPM_MM},1)
  105. ENABLE_SVE_FOR_NS := 0
  106. ENABLE_SME_FOR_NS := 0
  107. else
  108. ENABLE_SVE_FOR_NS := 2
  109. ENABLE_SME_FOR_NS := 2
  110. endif
  111. ifeq (${ENABLE_RME},1)
  112. BL31_SOURCES += plat/qemu/common/qemu_plat_attest_token.c \
  113. plat/qemu/common/qemu_realm_attest_key.c
  114. endif
  115. # Treating this as a memory-constrained port for now
  116. USE_COHERENT_MEM := 0
  117. # This can be overridden depending on CPU(s) used in the QEMU image
  118. HW_ASSISTED_COHERENCY := 1
  119. CTX_INCLUDE_AARCH32_REGS := 0
  120. ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
  121. $(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
  122. endif
  123. # Pointer Authentication sources
  124. ifeq (${ENABLE_PAUTH}, 1)
  125. PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c
  126. CTX_INCLUDE_PAUTH_REGS := 1
  127. endif
  128. endif