platform.mk 3.4 KB

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  1. #
  2. # Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
  3. #
  4. # SPDX-License-Identifier: BSD-3-Clause
  5. #
  6. override PROGRAMMABLE_RESET_ADDRESS := 1
  7. override USE_COHERENT_MEM := 1
  8. override SEPARATE_CODE_AND_RODATA := 1
  9. override ENABLE_SVE_FOR_NS := 0
  10. # Enable workarounds for selected Cortex-A53 erratas.
  11. ERRATA_A53_855873 := 1
  12. ifeq (${RESET_TO_BL31}, 1)
  13. override RESET_TO_BL31 := 1
  14. override TRUSTED_BOARD_BOOT := 0
  15. SQ_USE_SCMI_DRIVER ?= 0
  16. else
  17. override RESET_TO_BL31 := 0
  18. override RESET_TO_BL2 := 1
  19. SQ_USE_SCMI_DRIVER := 1
  20. BL2_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
  21. endif
  22. # Libraries
  23. include lib/xlat_tables_v2/xlat_tables.mk
  24. PLAT_PATH := plat/socionext/synquacer
  25. PLAT_INCLUDES := -I$(PLAT_PATH)/include \
  26. -I$(PLAT_PATH)/drivers/scpi \
  27. -I$(PLAT_PATH)/drivers/mhu \
  28. -Idrivers/arm/css/scmi \
  29. -Idrivers/arm/css/scmi/vendor
  30. PLAT_BL_COMMON_SOURCES += $(PLAT_PATH)/sq_helpers.S \
  31. drivers/arm/pl011/aarch64/pl011_console.S \
  32. drivers/delay_timer/delay_timer.c \
  33. drivers/delay_timer/generic_delay_timer.c \
  34. lib/cpus/aarch64/cortex_a53.S \
  35. $(PLAT_PATH)/sq_xlat_setup.c \
  36. ${XLAT_TABLES_LIB_SRCS}
  37. # Include GICv3 driver files
  38. include drivers/arm/gic/v3/gicv3.mk
  39. ifneq (${RESET_TO_BL31}, 1)
  40. BL2_SOURCES += common/desc_image_load.c \
  41. drivers/io/io_fip.c \
  42. drivers/io/io_memmap.c \
  43. drivers/io/io_storage.c \
  44. $(PLAT_PATH)/sq_bl2_setup.c \
  45. $(PLAT_PATH)/sq_image_desc.c \
  46. $(PLAT_PATH)/sq_io_storage.c
  47. ifeq (${TRUSTED_BOARD_BOOT},1)
  48. include drivers/auth/mbedtls/mbedtls_crypto.mk
  49. include drivers/auth/mbedtls/mbedtls_x509.mk
  50. BL2_SOURCES += drivers/auth/auth_mod.c \
  51. drivers/auth/crypto_mod.c \
  52. drivers/auth/img_parser_mod.c \
  53. drivers/auth/tbbr/tbbr_cot_common.c \
  54. drivers/auth/tbbr/tbbr_cot_bl2.c \
  55. plat/common/tbbr/plat_tbbr.c \
  56. $(PLAT_PATH)/sq_rotpk.S \
  57. $(PLAT_PATH)/sq_tbbr.c
  58. ROT_KEY = $(BUILD_PLAT)/rot_key.pem
  59. ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
  60. $(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
  61. $(BUILD_PLAT)/bl2/sq_rotpk.o: $(ROTPK_HASH)
  62. certificates: $(ROT_KEY)
  63. $(ROT_KEY): | $$(@D)/
  64. $(s)echo " OPENSSL $@"
  65. $(q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
  66. $(ROTPK_HASH): $(ROT_KEY) | $$(@D)/
  67. $(s)echo " OPENSSL $@"
  68. $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
  69. ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
  70. endif # TRUSTED_BOARD_BOOT
  71. endif
  72. BL31_SOURCES += drivers/arm/ccn/ccn.c \
  73. ${GICV3_SOURCES} \
  74. plat/common/plat_gicv3.c \
  75. plat/common/plat_psci_common.c \
  76. $(PLAT_PATH)/sq_bl31_setup.c \
  77. $(PLAT_PATH)/sq_ccn.c \
  78. $(PLAT_PATH)/sq_topology.c \
  79. $(PLAT_PATH)/sq_psci.c \
  80. $(PLAT_PATH)/sq_gicv3.c \
  81. $(PLAT_PATH)/drivers/scp/sq_scp.c
  82. ifeq (${SQ_USE_SCMI_DRIVER},0)
  83. BL31_SOURCES += $(PLAT_PATH)/drivers/scpi/sq_scpi.c \
  84. $(PLAT_PATH)/drivers/mhu/sq_mhu.c
  85. else
  86. BL31_SOURCES += $(PLAT_PATH)/drivers/scp/sq_scmi.c \
  87. drivers/arm/css/scmi/scmi_common.c \
  88. drivers/arm/css/scmi/scmi_pwr_dmn_proto.c \
  89. drivers/arm/css/scmi/scmi_sys_pwr_proto.c \
  90. drivers/arm/css/scmi/vendor/scmi_sq.c \
  91. drivers/arm/css/mhu/css_mhu_doorbell.c
  92. endif
  93. ifeq (${SPM_MM},1)
  94. $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
  95. BL31_SOURCES += $(PLAT_PATH)/sq_spm.c
  96. endif
  97. ifeq (${SQ_USE_SCMI_DRIVER},1)
  98. $(eval $(call add_define,SQ_USE_SCMI_DRIVER))
  99. endif