Home Explore Help
Sign In
OWEALs
/
arm-trusted-firmware
mirror of https://github.com/ARM-software/arm-trusted-firmware
2
0
Fork 0
Files Issues 1 Wiki
Branch: master
Branches Tags
arm-trusted-fir...
/
services
/
std_svc
/
spm
/
common
/
aarch64
/
spm_shim_exceptions.S

spm_shim_exceptions.S 3.1 KB
Permalink History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128 
  1. /*
    2. 

  2.  * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #include <arch.h>
    8. 

  8. #include <asm_macros.S>
    9. 

  9. #include <common/bl_common.h>
    10. 

  10. #include <context.h>
    11. 

  11. 

  12. /* -----------------------------------------------------------------------------
    13. 

  13.  * Very simple stackless exception handlers used by the spm shim layer.
    14. 

  14.  * -----------------------------------------------------------------------------
    15. 

  15.  */
    16. 

  16. 	.globl	spm_shim_exceptions_ptr
    17. 

  17. 

  18. vector_base spm_shim_exceptions_ptr, .spm_shim_exceptions
    19. 

  19. 

  20. 	/* -----------------------------------------------------
    21. 

  21. 	 * Current EL with SP0 : 0x0 - 0x200
    22. 

  22. 	 * -----------------------------------------------------
    23. 

  23. 	 */
    24. 

  24. vector_entry SynchronousExceptionSP0, .spm_shim_exceptions
    25. 

  25. 	b	.
    26. 

  26. end_vector_entry SynchronousExceptionSP0
    27. 

  27. 

  28. vector_entry IrqSP0, .spm_shim_exceptions
    29. 

  29. 	b	.
    30. 

  30. end_vector_entry IrqSP0
    31. 

  31. 

  32. vector_entry FiqSP0, .spm_shim_exceptions
    33. 

  33. 	b	.
    34. 

  34. end_vector_entry FiqSP0
    35. 

  35. 

  36. vector_entry SErrorSP0, .spm_shim_exceptions
    37. 

  37. 	b	.
    38. 

  38. end_vector_entry SErrorSP0
    39. 

  39. 

  40. 	/* -----------------------------------------------------
    41. 

  41. 	 * Current EL with SPx: 0x200 - 0x400
    42. 

  42. 	 * -----------------------------------------------------
    43. 

  43. 	 */
    44. 

  44. vector_entry SynchronousExceptionSPx, .spm_shim_exceptions
    45. 

  45. 	b	.
    46. 

  46. end_vector_entry SynchronousExceptionSPx
    47. 

  47. 

  48. vector_entry IrqSPx, .spm_shim_exceptions
    49. 

  49. 	b	.
    50. 

  50. end_vector_entry IrqSPx
    51. 

  51. 

  52. vector_entry FiqSPx, .spm_shim_exceptions
    53. 

  53. 	b	.
    54. 

  54. end_vector_entry FiqSPx
    55. 

  55. 

  56. vector_entry SErrorSPx, .spm_shim_exceptions
    57. 

  57. 	b	.
    58. 

  58. end_vector_entry SErrorSPx
    59. 

  59. 

  60. 	/* -----------------------------------------------------
    61. 

  61. 	 * Lower EL using AArch64 : 0x400 - 0x600. No exceptions
    62. 

  62. 	 * are handled since secure_partition does not implement
    63. 

  63. 	 * a lower EL
    64. 

  64. 	 * -----------------------------------------------------
    65. 

  65. 	 */
    66. 

  66. vector_entry SynchronousExceptionA64, .spm_shim_exceptions
    67. 

  67. 	msr	tpidr_el1, x30
    68. 

  68. 	mrs	x30, esr_el1
    69. 

  69. 	ubfx	x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
    70. 

  70. 

  71. 	cmp	x30, #EC_AARCH64_SVC
    72. 

  72. 	b.eq 	do_smc
    73. 

  73. 

  74. 	cmp	x30, #EC_AARCH32_SVC
    75. 

  75. 	b.eq	do_smc
    76. 

  76. 

  77. 	cmp	x30, #EC_AARCH64_SYS
    78. 

  78. 	b.eq	handle_sys_trap
    79. 

  79. 

  80. 	/* Fail in all the other cases */
    81. 

  81. 	b	panic
    82. 

  82. 

  83. 	/* ---------------------------------------------
    84. 

  84. 	 * Tell SPM that we are done initialising
    85. 

  85. 	 * ---------------------------------------------
    86. 

  86. 	 */
    87. 

  87. do_smc:
    88. 

  88. 	mrs	x30, tpidr_el1
    89. 

  89. 	smc	#0
    90. 

  90. 	exception_return
    91. 

  91. 

  92. 	/* AArch64 system instructions trap are handled as a panic for now */
    93. 

  93. handle_sys_trap:
    94. 

  94. panic:
    95. 

  95. 	b	panic
    96. 

  96. end_vector_entry SynchronousExceptionA64
    97. 

  97. 

  98. vector_entry IrqA64, .spm_shim_exceptions
    99. 

  99. 	b	.
    100. 

  100. end_vector_entry IrqA64
    101. 

  101. 

  102. vector_entry FiqA64, .spm_shim_exceptions
    103. 

  103. 	b	.
    104. 

  104. end_vector_entry FiqA64
    105. 

  105. 

  106. vector_entry SErrorA64, .spm_shim_exceptions
    107. 

  107. 	b	.
    108. 

  108. end_vector_entry SErrorA64
    109. 

  109. 

  110. 	/* -----------------------------------------------------
    111. 

  111. 	 * Lower EL using AArch32 : 0x600 - 0x800
    112. 

  112. 	 * -----------------------------------------------------
    113. 

  113. 	 */
    114. 

  114. vector_entry SynchronousExceptionA32, .spm_shim_exceptions
    115. 

  115. 	b	.
    116. 

  116. end_vector_entry SynchronousExceptionA32
    117. 

  117. 

  118. vector_entry IrqA32, .spm_shim_exceptions
    119. 

  119. 	b	.
    120. 

  120. end_vector_entry IrqA32
    121. 

  121. 

  122. vector_entry FiqA32, .spm_shim_exceptions
    123. 

  123. 	b	.
    124. 

  124. end_vector_entry FiqA32
    125. 

  125. 

  126. vector_entry SErrorA32, .spm_shim_exceptions
    127. 

  127. 	b	.
    128. 

  128. end_vector_entry SErrorA32
    129.