tsp.ld.S 3.0 KB

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  1. /*
  2. * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <common/bl_common.ld.h>
  7. #include <lib/xlat_tables/xlat_tables_defs.h>
  8. OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
  9. OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
  10. ENTRY(tsp_entrypoint)
  11. MEMORY {
  12. RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
  13. }
  14. SECTIONS {
  15. RAM_REGION_START = ORIGIN(RAM);
  16. RAM_REGION_LENGTH = LENGTH(RAM);
  17. . = BL32_BASE;
  18. ASSERT(. == ALIGN(PAGE_SIZE),
  19. "BL32_BASE address is not aligned on a page boundary.")
  20. #if SEPARATE_CODE_AND_RODATA
  21. .text . : {
  22. __TEXT_START__ = .;
  23. *tsp_entrypoint.o(.text*)
  24. *(.text*)
  25. *(.vectors)
  26. __TEXT_END_UNALIGNED__ = .;
  27. . = ALIGN(PAGE_SIZE);
  28. __TEXT_END__ = .;
  29. } >RAM
  30. .rodata . : {
  31. __RODATA_START__ = .;
  32. *(.rodata*)
  33. RODATA_COMMON
  34. __RODATA_END_UNALIGNED__ = .;
  35. . = ALIGN(PAGE_SIZE);
  36. __RODATA_END__ = .;
  37. } >RAM
  38. #else /* SEPARATE_CODE_AND_RODATA */
  39. .ro . : {
  40. __RO_START__ = .;
  41. *tsp_entrypoint.o(.text*)
  42. *(.text*)
  43. *(.rodata*)
  44. RODATA_COMMON
  45. *(.vectors)
  46. __RO_END_UNALIGNED__ = .;
  47. /*
  48. * Memory page(s) mapped to this section will be marked as read-only,
  49. * executable. No RW data from the next section must creep in. Ensure
  50. * that the rest of the current memory page is unused.
  51. */
  52. . = ALIGN(PAGE_SIZE);
  53. __RO_END__ = .;
  54. } >RAM
  55. #endif /* SEPARATE_CODE_AND_RODATA */
  56. __RW_START__ = .;
  57. DATA_SECTION >RAM
  58. RELA_SECTION >RAM
  59. #ifdef TSP_PROGBITS_LIMIT
  60. ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
  61. #endif /* TSP_PROGBITS_LIMIT */
  62. STACK_SECTION >RAM
  63. BSS_SECTION >RAM
  64. XLAT_TABLE_SECTION >RAM
  65. #if USE_COHERENT_MEM
  66. /*
  67. * The base address of the coherent memory section must be page-aligned to
  68. * guarantee that the coherent data are stored on their own pages and are
  69. * not mixed with normal data. This is required to set up the correct memory
  70. * attributes for the coherent data page tables.
  71. */
  72. .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
  73. __COHERENT_RAM_START__ = .;
  74. *(.tzfw_coherent_mem)
  75. __COHERENT_RAM_END_UNALIGNED__ = .;
  76. /*
  77. * Memory page(s) mapped to this section will be marked as device
  78. * memory. No other unexpected data must creep in. Ensure that the rest
  79. * of the current memory page is unused.
  80. */
  81. . = ALIGN(PAGE_SIZE);
  82. __COHERENT_RAM_END__ = .;
  83. } >RAM
  84. #endif /* USE_COHERENT_MEM */
  85. __RW_END__ = .;
  86. __BL32_END__ = .;
  87. /DISCARD/ : {
  88. *(.dynsym .dynstr .hash .gnu.hash)
  89. }
  90. __BSS_SIZE__ = SIZEOF(.bss);
  91. #if USE_COHERENT_MEM
  92. __COHERENT_RAM_UNALIGNED_SIZE__ =
  93. __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
  94. #endif /* USE_COHERENT_MEM */
  95. ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
  96. RAM_REGION_END = .;
  97. }