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@@ -103,6 +103,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
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# define ARM_CPU_IMP_ARM 0x41
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# define HISI_CPU_IMP 0x48
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# define ARM_CPU_IMP_APPLE 0x61
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+# define ARM_CPU_IMP_MICROSOFT 0x6D
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# define ARM_CPU_PART_CORTEX_A72 0xD08
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# define ARM_CPU_PART_N1 0xD0C
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@@ -124,6 +125,8 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
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# define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
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# define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
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+# define MICROSOFT_CPU_PART_COBALT_100 0xD49
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+
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# define MIDR_PARTNUM_SHIFT 4
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# define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT)
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# define MIDR_PARTNUM(midr) \
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