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+#! /usr/bin/env perl
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+# This file is dual-licensed, meaning that you can use it under your
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+# choice of either of the following two licenses:
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+#
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+# Copyright 2023-2023 The OpenSSL Project Authors. All Rights Reserved.
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+#
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+# Licensed under the Apache License 2.0 (the "License"). You may not use
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+# this file except in compliance with the License. You can obtain a copy
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+# in the file LICENSE in the source distribution or at
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+# https://www.openssl.org/source/license.html
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+#
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+# or
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+#
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+# Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com>
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+# All rights reserved.
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+#
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+# Redistribution and use in source and binary forms, with or without
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+# modification, are permitted provided that the following conditions
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+# are met:
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+# 1. Redistributions of source code must retain the above copyright
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+# notice, this list of conditions and the following disclaimer.
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+# 2. Redistributions in binary form must reproduce the above copyright
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+# notice, this list of conditions and the following disclaimer in the
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+# documentation and/or other materials provided with the distribution.
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+#
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+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+
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+# - RV64I
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+# - RISC-V Vector ('V') with VLEN >= 128
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+# - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
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+# - RISC-V Zicclsm(Main memory supports misaligned loads/stores)
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+
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+use strict;
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+use warnings;
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+
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+use FindBin qw($Bin);
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+use lib "$Bin";
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+use lib "$Bin/../../perlasm";
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+use riscv;
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+
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+# $output is the last argument if it looks like a file (it has an extension)
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+# $flavour is the first argument if it doesn't look like a file
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+my $output = $#ARGV >= 0 && $ARGV[$#ARGV] =~ m|\.\w+$| ? pop : undef;
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+my $flavour = $#ARGV >= 0 && $ARGV[0] !~ m|\.| ? shift : undef;
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+
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+$output and open STDOUT, ">$output";
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+
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+my $code = <<___;
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+.text
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+___
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+
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+# void ChaCha20_ctr32_zvkb(unsigned char *out, const unsigned char *inp,
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+# size_t len, const unsigned int key[8],
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+# const unsigned int counter[4]);
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+################################################################################
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+my ( $OUTPUT, $INPUT, $LEN, $KEY, $COUNTER ) = ( "a0", "a1", "a2", "a3", "a4" );
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+my ( $T0 ) = ( "t0" );
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+my ( $CONST_DATA0, $CONST_DATA1, $CONST_DATA2, $CONST_DATA3 ) =
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+ ( "a5", "a6", "a7", "t1" );
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+my ( $KEY0, $KEY1, $KEY2,$KEY3, $KEY4, $KEY5, $KEY6, $KEY7,
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+ $COUNTER0, $COUNTER1, $NONCE0, $NONCE1
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+) = ( "s0", "s1", "s2", "s3", "s4", "s5", "s6",
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+ "s7", "s8", "s9", "s10", "s11" );
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+my ( $VL, $STRIDE, $CHACHA_LOOP_COUNT ) = ( "t2", "t3", "t4" );
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+my (
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+ $V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7, $V8, $V9, $V10,
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+ $V11, $V12, $V13, $V14, $V15, $V16, $V17, $V18, $V19, $V20, $V21,
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+ $V22, $V23, $V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
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+) = map( "v$_", ( 0 .. 31 ) );
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+
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+sub chacha_quad_round_group {
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+ my (
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+ $A0, $B0, $C0, $D0, $A1, $B1, $C1, $D1,
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+ $A2, $B2, $C2, $D2, $A3, $B3, $C3, $D3
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+ ) = @_;
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+
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+ my $code = <<___;
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+ # a += b; d ^= a; d <<<= 16;
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+ @{[vadd_vv $A0, $A0, $B0]}
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+ @{[vadd_vv $A1, $A1, $B1]}
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+ @{[vadd_vv $A2, $A2, $B2]}
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+ @{[vadd_vv $A3, $A3, $B3]}
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+ @{[vxor_vv $D0, $D0, $A0]}
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+ @{[vxor_vv $D1, $D1, $A1]}
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+ @{[vxor_vv $D2, $D2, $A2]}
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+ @{[vxor_vv $D3, $D3, $A3]}
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+ @{[vror_vi $D0, $D0, 32 - 16]}
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+ @{[vror_vi $D1, $D1, 32 - 16]}
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+ @{[vror_vi $D2, $D2, 32 - 16]}
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+ @{[vror_vi $D3, $D3, 32 - 16]}
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+ # c += d; b ^= c; b <<<= 12;
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+ @{[vadd_vv $C0, $C0, $D0]}
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+ @{[vadd_vv $C1, $C1, $D1]}
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+ @{[vadd_vv $C2, $C2, $D2]}
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+ @{[vadd_vv $C3, $C3, $D3]}
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+ @{[vxor_vv $B0, $B0, $C0]}
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+ @{[vxor_vv $B1, $B1, $C1]}
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+ @{[vxor_vv $B2, $B2, $C2]}
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+ @{[vxor_vv $B3, $B3, $C3]}
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+ @{[vror_vi $B0, $B0, 32 - 12]}
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+ @{[vror_vi $B1, $B1, 32 - 12]}
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+ @{[vror_vi $B2, $B2, 32 - 12]}
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+ @{[vror_vi $B3, $B3, 32 - 12]}
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+ # a += b; d ^= a; d <<<= 8;
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+ @{[vadd_vv $A0, $A0, $B0]}
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+ @{[vadd_vv $A1, $A1, $B1]}
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+ @{[vadd_vv $A2, $A2, $B2]}
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+ @{[vadd_vv $A3, $A3, $B3]}
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+ @{[vxor_vv $D0, $D0, $A0]}
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+ @{[vxor_vv $D1, $D1, $A1]}
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+ @{[vxor_vv $D2, $D2, $A2]}
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+ @{[vxor_vv $D3, $D3, $A3]}
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+ @{[vror_vi $D0, $D0, 32 - 8]}
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+ @{[vror_vi $D1, $D1, 32 - 8]}
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+ @{[vror_vi $D2, $D2, 32 - 8]}
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+ @{[vror_vi $D3, $D3, 32 - 8]}
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+ # c += d; b ^= c; b <<<= 7;
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+ @{[vadd_vv $C0, $C0, $D0]}
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+ @{[vadd_vv $C1, $C1, $D1]}
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+ @{[vadd_vv $C2, $C2, $D2]}
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+ @{[vadd_vv $C3, $C3, $D3]}
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+ @{[vxor_vv $B0, $B0, $C0]}
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+ @{[vxor_vv $B1, $B1, $C1]}
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+ @{[vxor_vv $B2, $B2, $C2]}
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+ @{[vxor_vv $B3, $B3, $C3]}
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+ @{[vror_vi $B0, $B0, 32 - 7]}
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+ @{[vror_vi $B1, $B1, 32 - 7]}
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+ @{[vror_vi $B2, $B2, 32 - 7]}
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+ @{[vror_vi $B3, $B3, 32 - 7]}
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+___
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+
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+ return $code;
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+}
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+
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+$code .= <<___;
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+.p2align 3
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+.globl ChaCha20_ctr32_zvkb
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+.type ChaCha20_ctr32_zvkb,\@function
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+ChaCha20_ctr32_zvkb:
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+ srli $LEN, $LEN, 6
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+ beqz $LEN, .Lend
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+
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+ addi sp, sp, -96
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+ sd s0, 0(sp)
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+ sd s1, 8(sp)
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+ sd s2, 16(sp)
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+ sd s3, 24(sp)
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+ sd s4, 32(sp)
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+ sd s5, 40(sp)
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+ sd s6, 48(sp)
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+ sd s7, 56(sp)
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+ sd s8, 64(sp)
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+ sd s9, 72(sp)
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+ sd s10, 80(sp)
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+ sd s11, 88(sp)
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+
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+ li $STRIDE, 64
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+
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+ #### chacha block data
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+ # "expa" little endian
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+ li $CONST_DATA0, 0x61707865
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+ # "nd 3" little endian
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+ li $CONST_DATA1, 0x3320646e
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+ # "2-by" little endian
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+ li $CONST_DATA2, 0x79622d32
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+ # "te k" little endian
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+ li $CONST_DATA3, 0x6b206574
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+
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+ lw $KEY0, 0($KEY)
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+ lw $KEY1, 4($KEY)
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+ lw $KEY2, 8($KEY)
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+ lw $KEY3, 12($KEY)
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+ lw $KEY4, 16($KEY)
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+ lw $KEY5, 20($KEY)
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+ lw $KEY6, 24($KEY)
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+ lw $KEY7, 28($KEY)
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+
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+ lw $COUNTER0, 0($COUNTER)
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+ lw $COUNTER1, 4($COUNTER)
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+ lw $NONCE0, 8($COUNTER)
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+ lw $NONCE1, 12($COUNTER)
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+
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+.Lblock_loop:
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+ @{[vsetvli $VL, $LEN, "e32", "m1", "ta", "ma"]}
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+
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+ # init chacha const states
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+ @{[vmv_v_x $V0, $CONST_DATA0]}
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+ @{[vmv_v_x $V1, $CONST_DATA1]}
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+ @{[vmv_v_x $V2, $CONST_DATA2]}
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+ @{[vmv_v_x $V3, $CONST_DATA3]}
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+
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+ # init chacha key states
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+ @{[vmv_v_x $V4, $KEY0]}
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+ @{[vmv_v_x $V5, $KEY1]}
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+ @{[vmv_v_x $V6, $KEY2]}
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+ @{[vmv_v_x $V7, $KEY3]}
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+ @{[vmv_v_x $V8, $KEY4]}
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+ @{[vmv_v_x $V9, $KEY5]}
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+ @{[vmv_v_x $V10, $KEY6]}
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+ @{[vmv_v_x $V11, $KEY7]}
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+
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+ # init chacha key states
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+ @{[vid_v $V12]}
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+ @{[vadd_vx $V12, $V12, $COUNTER0]}
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+ @{[vmv_v_x $V13, $COUNTER1]}
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+
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+ # init chacha nonce states
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+ @{[vmv_v_x $V14, $NONCE0]}
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+ @{[vmv_v_x $V15, $NONCE1]}
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+
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+ # load the top-half of input data
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+ @{[vlsseg_nf_e32_v 8, $V16, $INPUT, $STRIDE]}
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+
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+ li $CHACHA_LOOP_COUNT, 10
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+.Lround_loop:
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+ addi $CHACHA_LOOP_COUNT, $CHACHA_LOOP_COUNT, -1
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+ @{[chacha_quad_round_group
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+ $V0, $V4, $V8, $V12,
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+ $V1, $V5, $V9, $V13,
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+ $V2, $V6, $V10, $V14,
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+ $V3, $V7, $V11, $V15]}
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+ @{[chacha_quad_round_group
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+ $V0, $V5, $V10, $V15,
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+ $V1, $V6, $V11, $V12,
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+ $V2, $V7, $V8, $V13,
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+ $V3, $V4, $V9, $V14]}
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+ bnez $CHACHA_LOOP_COUNT, .Lround_loop
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+
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+ # load the bottom-half of input data
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+ addi $T0, $INPUT, 32
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+ @{[vlsseg_nf_e32_v 8, $V24, $T0, $STRIDE]}
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+
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+ # add chacha top-half initial block states
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+ @{[vadd_vx $V0, $V0, $CONST_DATA0]}
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+ @{[vadd_vx $V1, $V1, $CONST_DATA1]}
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+ @{[vadd_vx $V2, $V2, $CONST_DATA2]}
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+ @{[vadd_vx $V3, $V3, $CONST_DATA3]}
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+ @{[vadd_vx $V4, $V4, $KEY0]}
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+ @{[vadd_vx $V5, $V5, $KEY1]}
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+ @{[vadd_vx $V6, $V6, $KEY2]}
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+ @{[vadd_vx $V7, $V7, $KEY3]}
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+ # xor with the top-half input
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+ @{[vxor_vv $V16, $V16, $V0]}
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+ @{[vxor_vv $V17, $V17, $V1]}
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+ @{[vxor_vv $V18, $V18, $V2]}
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+ @{[vxor_vv $V19, $V19, $V3]}
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+ @{[vxor_vv $V20, $V20, $V4]}
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+ @{[vxor_vv $V21, $V21, $V5]}
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+ @{[vxor_vv $V22, $V22, $V6]}
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+ @{[vxor_vv $V23, $V23, $V7]}
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+
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+ # save the top-half of output
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+ @{[vssseg_nf_e32_v 8, $V16, $OUTPUT, $STRIDE]}
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+
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+ # add chacha bottom-half initial block states
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+ @{[vadd_vx $V8, $V8, $KEY4]}
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+ @{[vadd_vx $V9, $V9, $KEY5]}
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+ @{[vadd_vx $V10, $V10, $KEY6]}
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+ @{[vadd_vx $V11, $V11, $KEY7]}
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+ @{[vid_v $V0]}
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+ @{[vadd_vx $V12, $V12, $COUNTER0]}
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+ @{[vadd_vx $V13, $V13, $COUNTER1]}
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+ @{[vadd_vx $V14, $V14, $NONCE0]}
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+ @{[vadd_vx $V15, $V15, $NONCE1]}
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+ @{[vadd_vv $V12, $V12, $V0]}
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+ # xor with the bottom-half input
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+ @{[vxor_vv $V24, $V24, $V8]}
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+ @{[vxor_vv $V25, $V25, $V9]}
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+ @{[vxor_vv $V26, $V26, $V10]}
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+ @{[vxor_vv $V27, $V27, $V11]}
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+ @{[vxor_vv $V29, $V29, $V13]}
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+ @{[vxor_vv $V28, $V28, $V12]}
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+ @{[vxor_vv $V30, $V30, $V14]}
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+ @{[vxor_vv $V31, $V31, $V15]}
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+
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+ # save the bottom-half of output
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+ addi $T0, $OUTPUT, 32
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+ @{[vssseg_nf_e32_v 8, $V24, $T0, $STRIDE]}
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+
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+ # update counter
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+ add $COUNTER0, $COUNTER0, $VL
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+ sub $LEN, $LEN, $VL
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+ # increase offset for `4 * 16 * VL = 64 * VL`
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+ slli $T0, $VL, 6
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+ add $INPUT, $INPUT, $T0
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+ add $OUTPUT, $OUTPUT, $T0
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+ bnez $LEN, .Lblock_loop
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+
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+ ld s0, 0(sp)
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+ ld s1, 8(sp)
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+ ld s2, 16(sp)
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+ ld s3, 24(sp)
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+ ld s4, 32(sp)
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+ ld s5, 40(sp)
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+ ld s6, 48(sp)
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+ ld s7, 56(sp)
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+ ld s8, 64(sp)
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+ ld s9, 72(sp)
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+ ld s10, 80(sp)
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+ ld s11, 88(sp)
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+ addi sp, sp, 96
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+
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+.Lend:
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+ ret
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+.size ChaCha20_ctr32_zvkb,.-ChaCha20_ctr32_zvkb
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+___
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+
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+print $code;
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+
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+close STDOUT or die "error closing STDOUT: $!";
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