Jerry Shih
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da8b6308bd
Use scalar ALU and vector ALU together for chacha20 stream cipher
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hai 8 meses |
Jerry Shih
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3e56c0efe7
riscv: Provide vector crypto implementation of AES-128/256-XTS mode.
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hai 1 ano |
Jerry Shih
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3645eb0be2
Update for Zvkb extension.
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hai 1 ano |
Phoebe Chen
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216424e18d
riscv: Add RISC-V Vector opcode in riscv.pm
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hai 1 ano |
Charalampos Mitrodimas
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f20ee1f490
riscv: SM3: Provide a Zvksh-based implementation
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hai 1 ano |
Christoph Müllner
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7543bb3a69
riscv: SM4: Provide a Zvksed-based implementation
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hai 1 ano |
Charalampos Mitrodimas
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9c22a240da
riscv: sha512: Provide a Zvknhb-based implementation
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hai 1 ano |
Charalampos Mitrodimas
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1707306652
riscv: sha256: Provide a Zvknha-based implementation
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hai 1 ano |
Christoph Müllner
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f6631e38f9
riscv: AES: Provide a Zvkned-based implementation
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hai 1 ano |
Christoph Müllner
|
5191bcc816
riscv: GCM: Provide a Zvkg-based implementation
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hai 1 ano |
Christoph Müllner
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003f569814
riscv: GCM: Provide a Zvbb/Zvbc-based implementation
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hai 1 ano |
Heiko Stuebner
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3e76b38852
riscv: Clarify dual-licensing wording for GCM and AES
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hai 1 ano |
Heiko Stuebner
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33523d6d66
riscv: GCM: dual-license under Apache + 2-clause BSD
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hai 1 ano |
Christoph Müllner
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b24684369b
riscv: GCM: Simplify GCM calculation
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hai 1 ano |
Christoph Müllner
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75623ed8d0
riscv: GCM: Use riscv.pm
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hai 1 ano |
Christoph Müllner
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ac97cd6005
riscv.pm: Add improved error messages to read_reg code
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hai 1 ano |
Christoph Müllner
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c8a641c39f
riscv: aes: Move reusable Perl code into Perl module
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hai 1 ano |